面向物联网领域的低成本ECC密码处理器设计  

Design of low⁃cost ECC processor for IoT domain

作　　者：马敬万 曲英杰[1] MA Jingwan;QU Yingjie(College of Information Science and Technology,Qingdao University of Science and Technology,Qingdao 266061,China)

机构地区：[1]青岛科技大学信息科学技术学院,山东青岛266061

出　　处：《现代电子技术》2024年第18期95-100,共6页Modern Electronics Technique

摘　　要：为了保障物联网设备的隐私和安全,同时更好地满足其资源受限的特性,采用椭圆曲线密码(ECC)算法方案,通过优化底层算法和电路结构,设计了基于加法器的低成本架构的点乘硬件电路。采用硬件复用技术来减少资源消耗,每个模运算电路只用一个超前进位加法器;优化模运算算子调度,改进电路结构,点运算只使用两个模加减模块、一个模逆模块和一个模乘模块设计实现。在Xilinx公司XCZU3CG-SFVC784-1-E的FPGA平台上进行分析,该点乘电路共使用了8927个CLB LUTs,7789个CLB Registers,电路总功耗为0.371W,工作频率可达247.3 MHz,对比其他架构,处理器硬件资源节省了39.10%~72.44%。In order to ensure the privacy and security of Internet of Things(IoTs)devices,and better meet the resource-limited characteristics,the elliptic curve cryptography(ECC)algorithm scheme is used to design a low-cost architecture for a dot multiplication hardware circuit based on the adder by optimizing the underlying algorithm and circuit structure.Hardware resource consumption is minimized by means of hardware reuse technology,with each modular arithmetic circuit using only one carry-save adder.By optimizing modular arithmetic operator scheduling and improving circuit structure,point operations are designed and implemented using only two modular addition and subtraction modules,one modular inverse module and one modular multiplication module.The analysis are conducted on Xilinx′s XCZU3CG-SFVC784-1-E FPGA platform,a total of 8927 CLB LUTs and 7789 CLB Registers are used in the dot multiplication circuit,with a total power consumption of 0.371 W and an operating frequency of 247.3 MHz.In comparison with other architectures,the processor hardware resources are saved from 39.10%to 72.44%.

关 键 词：物联网 椭圆曲线密码 密码处理器 模运算 硬件复用 FPGA 

分 类 号：TN919-34[电子电信—通信与信息系统] TN492-34[电子电信—信息与通信工程]