ACF-COG芯片互连电阻建模与工艺参数优化  

Modeling of ACF-COG Interconnection Resistance and Optimization of Process Parameters

作　　者：陈睿卿 刘磊[1] 贾磊 罗晨[1] 周怡君[1] CHEN Ruiqing;LIU Lei;JIA Lei;LUO Chen;ZHOU Yijun(School of Mechanical Eng.,Southeast Univ.,Nanjing 211189,China;Wuxi Shangshi Electronic Technol.Co.,Ltd.,Wuxi 214000,China)

机构地区：[1]东南大学机械工程学院,江苏南京211189 [2]无锡尚实电子科技有限公司,江苏无锡214000

出　　处：《工程科学与技术》2024年第5期277-286,共10页Advanced Engineering Sciences

基　　金：国家自然科学基金资助项目(51975119);无锡市“太湖之光”科技攻关(产业前瞻及关键技术研发)项目(G20222011)。

摘　　要：玻璃覆晶封装技术是液晶显示器生产过程中的核心技术,主要采用热固性固化胶和若干导电颗粒组成各向异性导电胶膜倒装实现互连,而互连后的芯片电阻是材料选择与工艺参数的重要评估指标。本文旨在建立芯片互连电阻仿真体系并探究相同导电颗粒分布下芯片封装的最优工艺参数。首先,通过大量实验获取采用CP6530ID型号各向异性导电胶膜的芯片在不同工艺参数下的凸点互连电阻及凸点捕捉到的导电颗粒数目,并对实验数据进行统计分析。其次,在数值模拟实验中,为模拟键合温度与压力的耦合方式,采用顺序热力耦合方法。在得到热力耦合场下CP6530ID型号各向异性导电胶膜中导电颗粒的形变量后,通过建立的导电颗粒互连电阻的数学模型算出芯片互连电阻,将互连电阻计算结果与实验结果对比,验证仿真结果的有效性及对实验的指导意义。最后,将生产商索尼化学公司推荐的封装工艺参数范围作为优化起点,对随机化导电颗粒分布情况进行仿真,以仿真结果为参考探究芯片封装的最优工艺参数。在实现芯片有效封装的前提下,仿真结果显示,键合温度为190℃、键合压力为100MPa时,芯片互连电阻最小。芯片封装过程中,压力对互连电阻起决定性作用,温度对互连电阻的影响较为微弱。就压力因子而言,在不考虑导电颗粒被压裂的情况下,压力越大,最后形成的互连电阻越小;温度越高,导电颗粒的热膨胀越剧烈,导致互连电阻越大。The chip-on-glass process is a core technology in the production of liquid crystal displays,primarily utilizing thermosetting curing glue and various conductive particles within anisotropic conductive adhesive film to achieve interconnection.The resistance of the chip after interconnection serves as a crucial evaluation index for material selection and process parameters.This study aims to establish a simulation system for chip interconnect resistance and to explore the optimal process parameters for chip packaging with a consistent distribution of conductive particles.In this regard,numerous experiments are conducted to determine the bump interconnection resistance of the chip using CP6530ID anisotropic conductive adhesive film under various process parameters and the number of conductive particles captured by the bump,with the experimental data undergoing statistical analysis.Subsequently,the sequential thermal-mechanical coupling method is utilized to simulate the coupling method of binding temperature and pressure.After determining the deformation variables of conductive particles in CP6530ID anisotropic conductive adhesive film under a thermodynamic coupling field,the chip interconnection resistance is calculated using the established mathematical model of conductive particle interconnection resistance,and the interconnection resistance calculation results are compared with experimental results to verify the validity of the simulation results and the guiding significance of the experiment.The optimization starting point is based on the packaging process parameter range recommended by Sony Chemical.By randomizing the distribution of conductive particles,the study explored the optimal process parameters for chip packaging,using the simulation results as a reference.The findings indicate that under effective chip packaging conditions,the chip interconnect resistance is minimized at a binding temperature of 190℃and a binding pressure of 100 MPa.During the chip packaging process,pressure is a decisive factor in

关 键 词：液晶显示器 玻璃覆晶封装 数值模拟 互连电阻 工艺参数 

分 类 号：TN405[电子电信—微电子学与固体电子学]