基于LVDS的DC平衡技术的高可靠性传输系统设计  

High reliability transmission system design based on LVDS DC balancing technology

作　　者：邓惠祯 吴柯锐 张晓雪[1] 赵志雄 Deng Huizhen;Wu Kerui;Zhang Xiaoxue;Zhao Zhixiong(State Key Laboratory of Dynamic Measurement Technology,North University of China,Taiyuan 030051,China;Unit 93160 of PLA,Beijing 100076,China)

机构地区：[1]中北大学省部共建动态测试技术国家重点实验室,太原030051 [2]中国人民解放军93160部队,北京100076

出　　处：《国外电子测量技术》2024年第8期103-109,共7页Foreign Electronic Measurement Technology

基　　金：山西省高校科技创新计划(2022L530);山西省基础研究计划青年项目基金(202303021222097)资助。

摘　　要：随着数据传输对速度、距离和可靠性要求的提高,同时考虑到工作人员在测试环境中的安全问题,提出一个基于低压差分信号(LVDS)的DC平衡技术的设计方案。该方案采用LVDS串化器SN65LV1023A和解串器SN65LV1224B作为发送和接收芯片,由于LVDS在长距离传输方面存在限制,因此在硬件设计中采用驱动器LMH0002TMA和均衡器LMH0024MA来增加信号的驱动能力和补偿信号的衰减;在外围电路中加入隔离器ADN4651和RCLamp3324P芯片,分别起到提供信号隔离和保护和为高速数据接口提供ESD保护的作用。同时软件设计中,在核心控制器FPGA内部加入8B/10B编码技术,以保证数据传输中的DC平衡,即数据流中连续出现的“1”/“0”达到一个平衡均匀的状态,降低误码率且提高数据的可靠性。经大量实验测试验证,此设计可在90 m双绞线上以300 Mbit/s速率零误码传输。With the increase of data transmission speed,distance and reliability requirements,and considering the safety of workers in the test environment,a design scheme of DC balancing technology based on LVDS is proposed in this paper.In this scheme,LVDS serializer SN65LV1023A and SN65LV1224B are used as sending and receiving chips.Due to the limitations of LVDS in long-distance transmission,therefore,the driver LMH0002TMA and equalizer LMH0024MA are used in the hardware design to increase the driving capacity of the signal and compensate the signal attenuation.The isolator ADN4651 and RCLamp3324P chips are added to the peripheral circuit to provide signal isolation and protection and ESD protection for the high-speed data interface.At the same time,in the software design,8B/10B coding technology is added to the core controller FPGA to ensure the DC balance in data transmission,that is the continuous"1"/"0"in the data stream reaches a balanced and even state,reduces the bit error rate and improves the reliability of the data.After a large number of experimental tests,this design can be transmitted on 90 m twisted pair at a rate of 300 Mbit/s with zero error.

关 键 词：LVDS DC平衡技术 高可靠性 8B/10B编码技术 

分 类 号：TN919[电子电信—通信与信息系统]