一种基于FPGA的多通道高速数据对齐装置设计与实现  

Design and Implementation of a Multi-Channel High-Speed Data Alignment Device Based on FPGA

作　　者：王晨曦 寇韵涵 WANG Chenxi;KOU Yunhan(NO.38 Research Institute of CETC,Hefei 230000)

机构地区：[1]中国电子科技集团公司第三十八研究所,合肥230000

出　　处：《火控雷达技术》2024年第3期96-100,共5页Fire Control Radar Technology

摘　　要：在现场可编程门阵列器件(FPGA)的高速实时信号处理系统中,利用多通道高速传输是一种常用的电路设计。由于多通道高速数据传输路径的不一致性,需要在接收端设计一种同步对齐装置。本文采用硬件编程语言设计了一种基于FPGA的多通道高速数据对齐装置,该装置具有控制逻辑清晰、结构简单、可扩展性强的特点。该装置主要包括FIFO时钟域转换模块,FIFO读写使能控制模块,主时钟域下数据对齐模块。Multi-channel data aligner is a common digital circuit in the high-speed and real-time signal processing systems with field programmable gate array(FPGA)architecture.Due to the inconsistency of multi-channel high-speed data transmission paths,a synchronous alignment device needed to be designed at the receiving end.In this paper,a multi-channel high-speed data alignment device based on FPGA was designed by using hardware programming language,which had the characteristics of clear control logic,simple structure and strong scalability.The device mainly included a FIFO clock domain conversion module,a FIFO read/write enabled control module,and a data alignment module in the master clock domain.

关 键 词：FPGA 多通道高速传输 同步对齐 

分 类 号：TN95[电子电信—信号与信息处理] TN972[电子电信—信息与通信工程]