一种用于常开型智能视觉感算系统的极速高精度模拟减法器  

Ultra High-speed High-precision Analog Subtractor Applied to Always-on Intelligent Visual Sense-computing System

作　　者：刘博 王想军 麦麦提·那扎买提 郑辞晏 向菲 魏琦[2] 杨兴华 乔飞[2] LIU Bo;WANG Xiangjun;NAZHAMAITI Maimaiti;ZHENG Ciyan;XIANG Fei;WEI Qi;YANG Xinghua;QIAO Fei(College of Information Engineering,Henan University of Science and Technology,Luoyang 471023,China;Tsinghua University,Beijing 100084,China;Guangdong Polytechnic Normal University,Guangzhou 510665,China;College of Science,Beijing Forestry University,Beijing 100091,China)

机构地区：[1]河南科技大学信息工程学院,洛阳471023 [2]清华大学,北京100084 [3]广东技术师范大学,广州510665 [4]北京林业大学理学院,北京100091

出　　处：《电子与信息学报》2024年第9期3807-3817,共11页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(92164203,62334006,61704049);新疆维吾尔自治区重点研发计划(2022B01008);河南省科技攻关计划(232102211066,242102211101);河南省高校青年骨干教师计划(2020GGJS077)。

摘　　要：常开型智能视觉感算系统对图像边缘特征提取的精度和实时性要求更高,其硬件能耗也随之暴增。采用模拟减法器代替传统数字处理在模拟域同步实现感知和边缘特征提取,可有效降低感存算一体系统的整体能耗,但与此同时,突破10^(–7)s数量级的长计算时间也成为了模拟减法器设计的瓶颈。该文提出一种新型的模拟减法运算电路结构,由模拟域的信号采样和减法运算两个功能电路组成。信号采样电路进一步由经改进的自举采样开关和采样电容组成;减法运算则由所提出的一种新型开关电容式模拟减法电路执行,可在2次采样时间内实现3次减法运算的高速并行处理。基于TSMC 180 nm/1.8 V CMOS工艺,完成整体模拟减法运算电路的设计。仿真实验结果表明,该减法器能够实现在模拟域中信号采样与计算的同步并行处理,一次并行处理的周期仅为20 ns,具备高速计算能力;减法器的计算取值范围宽至–900~900 mV,相对误差小于1.65%,最低仅为0.1%左右,处理精度高;电路能耗为25~27.8 pJ,处于中等可接受水平。综上,所提模拟减法器具备良好的速度、精度和能耗的性能平衡,可有效适用于高性能常开型智能视觉感知系统。Always-on intelligent visual sense-computing(Senputing)system has higher requirement on the accuracy and real-time of edge feature extraction on target image,and thus the accompanying hardware energy consumption increases accordingly.Since an analog subtracter can realize visual sensing and edge feature extraction synchronously in analogue domain instead of the traditional digital processing,the overall energy consumption of sensing-storage-computing integrated system can be effectively reduced.But meanwhile,the long calculation time beyond the order of 10~(–7)s has also become the bottleneck of design of analog subtracter circuits.A novel analogue subtraction circuit structure is proposed in this paper,which consists of two functional circuits in analogue domain:signal sampling and subtraction module.The signal sampling circuit is further composed of an improved bootstrapped sampling switch and a pair of sampling capacitors;The subtraction operation is performed by a novel switched capacitor analog subtraction circuit,which can realize high-speed parallel processing of three subtraction operations in two sampling times.Based on TSMC 180 nm/1.8 V CMOS technology,the design of the whole analog subtraction circuit is implemented.The simulation results show that,The proposed analog subtracter can realize synchronous parallel processing of signal sampling and computation in analogue domain,and the cycle of one parallel processing is only 20 ns,which has highspeed computing capability.The calculated value range of the subtracter is sufficiently wide from–900~900 mV,the relative error is less than 1.65%,the lowest one is only about 0.1%,which proves that the computing accuracy is high;The energy consumption is 25~27.8 pJ,which is in the acceptable medium level.Therefore,the proposed analog subtracter has a significant performance trade-off on speed,precision and energy consumption,and can be effectively applied to high-performance always-on intelligent visual senputing system.

关 键 词：模拟减法器 自举采样开关 电荷守恒定律 极速 高精度 

分 类 号：TN911.73[电子电信—通信与信息系统] TN492[电子电信—信息与通信工程]