一种基于冗余位结构CDAC的12 bit SAR ADC  

12 Bit SAR ADC Based on Redundant Bit Structure CDAC

作　　者：都文和[1] 韩波 宋昊洋 王梦梦 DU Wenhe;HAN Bo;SONG Haoyang;WANG Mengmeng(College of Communication and Electronic Engineering,Qiqihar University,Qiqihar 161006,China)

机构地区：[1]齐齐哈尔大学通信与电子工程学院,黑龙江齐齐哈尔161006

出　　处：《北华大学学报（自然科学版）》2024年第6期825-832,共8页Journal of Beihua University（Natural Science）

基　　金：黑龙江省省属本科高校基本科研业务费科研项目(XJ2022001802)。

摘　　要：提出一种基于非二进制冗余位结构CDAC的12 bit全差分逐次逼近型模拟数字转换器(SAR ADC)。传统SAR ADC中CDAC的单位电容数量随位数指数增长,且采用全差分结构的电容数量是单端结构的两倍,导致CDAC建立时间过长。为此,设计一种加入冗余位的分段式电容阵列,减少单位电容数量,提高CDAC建立速度。动态比较器的比较速度快,会导致数字码误判,通过加入冗余位弥补比较器对数字码误判的缺陷;采用底板采样技术,避免沟道电荷注入和时钟馈通,提高采样精度;采用SMIC 130 nm CMOS工艺。在电源电压1.2 V、20 MS/s采样率下,对1024点FFT仿真。结果显示:当输入频率(9.824 MHz)接近奈奎斯特频率时,该ADC的整体信噪失真比(SNDR)达到72.42 dB,有效位数(ENOB)达到11.73 bit;无杂散动态范围(SFDR)达到88.4 dBc,功耗为1.29 mW。12 bit fully differential successive approximation analog digital converter(SAR ADC)based on non-binary redundant bit structure CDAC is proposed.The number of unit capacitance of CDAC in traditional SAR ADC increases exponentially with the number of bits,and the total differential structure is twice that of single-ended structure,resulting in a long time for CDAC establishment.Therefore,a segmented capacitor array with redundant bits is designed to reduce the number of unit capacitors and increase the speed of CDAC establishment.Because the comparison speed of dynamic comparator is fast,it will lead to misjudgment of digital code,so redundant bits are added to make up for the error of logarithmic code of comparator.The backplane sampling technique is adopted to avoid channel charge injection and clock feed and improve sampling accuracy.SMIC 130 nm CMOS process is adopted.At the supply voltage of 1.2V and the sampling rate of 20 MS/s,1024 point FFT was simulated.The results show that when the input frequency(9.824 MHz)approaches the Nyquist frequency,the overall signal-to-noise ratio(SNDR)of the ADC reaches 72.42 dB and the effective bit(ENOB)reaches 11.73 bit.The spury-free dynamic range(SFDR)is 88.4 dBc and the power consumption is 1.29 mW.

关 键 词：逐次逼近型模数转换器 非二进制冗余位 分段电容 底板采样 

分 类 号：TN433[电子电信—微电子学与固体电子学]