基于PAM4信号的发送端分数间隔前馈均衡器设计  

Design of fractionally-spaced feed forward equalizer based on PAM4 signal at the transmitter

作　　者：卢明伟 张银行[1] LU Mingwei;ZHANG Yinhang(School of Communication and Electronic Engineering,Jishou University,Jishou 416000,China)

机构地区：[1]吉首大学通信与电子工程学院,湖南吉首416000

出　　处：《微电子学与计算机》2024年第10期82-88,共7页Microelectronics & Computer

基　　金：国家自然科学基金(61861019,62161012);湖南省教育厅科学研究项目(22B0525,21A0335);研究生校级科研项目(Jdy22020,TXJD202305)。

摘　　要：为了抑制18英寸FR4背板的高频损耗、提高传输速率,采用TSMC 0.18μm CMOS工艺设计了一种基于PAM4信号的发送端分数间隔前馈均衡器。该均衡器采用源极电容衰减延时单元来提高延时器的带宽,通过电容校准技术调节低频时的群延时,并同时采用电阻和电容校准技术来提高不同工艺角下群延时的平坦度。均衡器芯片的核心面积为0.427 mm×0.475 mm,功耗为258.6 mW。后仿真表明,两路5 Gbps的NRZ信号通过3抽头3T/4间隔的FFE均衡器和18英寸FR4背板传输后,可得到眼图水平张开达95 ps,垂直张开达30 mV的10 Gbps PAM4信号。In order to suppress the high frequency loss of the 18-inch FR4 backplane and improve the transmission rate,a fractionally-spaced feed forward equalizer(FFE)based on PAM4 signal was designed adopting TSMC 0.18μm CMOS technology.The bandwidth of the delay unit was boosted by source degeneration capacitance and the group delay at low frequency was adjusted by the technology of capacitance calibration.Meanwhile,the flatness of the group delay at different process corners was improved by the calibration technology of resistance and capacitance.The core area of the equalizer chip is 0.427 mm×0.475 mm and consumes a power of 258.6 mW.The post-simulation results show that the two-way 5 Gbps NRZ signals transmitted through FFE equalizer with 3-tap and 3T/4 spaced and 18-inch FR4 backplane,can get a 10 Gbps PAM4 signal eye diagram with 95 ps horizontal opening and of 30 mV vertical opening.

关 键 词：前馈均衡器 电容校准 群延时 眼图 

分 类 号：TN432[电子电信—微电子学与固体电子学]