低抖动快锁定10.9~12.0 GHz电荷泵锁相环  

Low-jitter fast-locked 10.9−12.0 GHz charge-pump phase-locked loop

作　　者：展永政 李仁刚 李拓 邹晓峰 周玉龙 胡庆生[2,3] 李连鸣 ZHAN Yongzheng;LI Rengang;LI Tuo;ZOU Xiaofeng;ZHOU Yulong;HU Qingsheng;LI Lianming(Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Limited Company,Jinan 250101,China;Institute of RF-and OE-ICs,Southeast University,Nanjing 210096,China;School of Information Science and Engineering,Southeast University,Nanjing 210096,China)

机构地区：[1]山东云海国创云计算装备产业创新中心有限公司,山东济南250101 [2]东南大学射频与光电集成电路研究所,江苏南京210096 [3]东南大学信息科学与工程学院,江苏南京210096

出　　处：《浙江大学学报（工学版）》2024年第11期2290-2298,共9页Journal of Zhejiang University：Engineering Science

基　　金：山东省自然科学基金资助项目(ZR2022QF146);山东省自然科学基金创新发展联合基金资助项目(ZR2023LZH004);中国博士后科学基金资助项目(2024M751268)。

摘　　要：基于65 nm CMOS工艺,设计适用于高速SerDes串行链路的低抖动高速电荷泵锁相环(CPPLL)电路.通过优化环路带宽以及压控振荡器(VCO)、电荷泵和鉴频鉴相器的电路结构,抑制电压纹波和内部噪声引起的抖动,以在满足SerDes链路需要的宽频范围和高速要求的同时,电荷泵锁相环能够获得较小的抖动偏差和稳定的时钟信号.包括整个焊盘在内的芯片面积为0.309 mm2.测试结果表明,电荷泵锁相环能够实现10.9~12 GHz的输出时钟信号,其在10 MHz频偏处的相位噪声、参考杂散和品质因数(FoM)分别为-111.47 dBc/Hz、-25.14 dBc和-223.5 dB.当输入参考频率为706.25 MHz时, CPPLL能够在600μs后输出稳定的11.3 GHz时钟信号,且RMS抖动为973.9 fs,约为0.065 UI.在电源电压为1.2 V下,电路的功耗为47.3 mW.所设计的锁相环(PLL)电路能够适用于20 Gb/s及以上的高速通信链路系统.A low-jitter high-speed charge-pump phase-locked loop(CPPLL)suitable for high-speed SerDes serial link was designed using 65 nm CMOS technology.Loop bandwidth and circuit structure of voltage-controlled oscillator(VCO),charge pump(CP),phase frequency detector(PFD)were optimized to reduce jitter caused by voltage ripple and internal noise.CPPLL can achieve a stable clock signal with the smaller jitter offset while meeting the wide frequency range and high speed requirements of SerDes link.Chip area including the entire pads is 0.309 mm2.The measurement results show that CPPLL can generate a 10.9-12 GHz clock signal and exhibit a phase noise of−111.47 dBc/Hz and a reference spur of−25.14 dBc and a figure-of-merit(FoM)of−223.5 dB at 10 MHz offset.It takes 600μs to generate a stable 11.3 GHz clock signal,and its RMS jitter is 973.9 fs when the reference frequency is 706.25 MHz,which is approximately 0.065 UI.The power consumption is 47.3 mW at the supply voltage of 1.2 V.The proposed phase-locked loop(PLL)is suitable for high-speed communication link systems at 20 Gb/s and above.

关 键 词：压控振荡器(VCO) 电荷泵 低抖动 串行链路 高速 

分 类 号：TN432[电子电信—微电子学与固体电子学]