基于两次时间内插的FPGA-TDC设计  

Design of a two-step time interpolation-based field-programmable gate array-time-to-digital converter

作　　者：陆江镕 李文昌[1,3] 刘剑 张天一[1] 王彦虎 LU Jiangrong;LI Wenchang;LIU Jian;ZHANG Tianyi;WANG Yanhu(Laboratory of Solid State Optoelectronic Information Technology,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China;College of Materials Science and Opto-Electronic Technology,University of Chinese Academy of Sciences,Beijing 100049,China;School of Integrated Circuits,University of Chinese Academy of Sciences,Beijing 100049,China;State Key Laboratory of Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China;Center of Materials Science and Optoelectronics Engineering,University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院半导体研究所固态光电信息技术实验室,北京100083 [2]中国科学院大学材料科学与光电技术学院,北京100049 [3]中国科学院大学集成电路学院,北京100049 [4]中国科学院半导体研究所半导体超晶格国家重点实验室,北京100083 [5]中国科学院大学材料与光电研究中心,北京100049

出　　处：《清华大学学报（自然科学版）》2024年第10期1809-1817,共9页Journal of Tsinghua University(Science and Technology)

摘　　要：减少基于现场可编程门阵列实现的时间数字转换器(FPGA-TDC)中延迟单元的延迟时间,可以提高TDC分辨率,但是需要构建更长的抽头延迟链,使延迟单元积累更多的非线性,导致系统线性度恶化。该文在粗计数与细计数结合架构的基础上,利用Xilinx Virtex UltraScale+FPGA平台设计出一种基于两次时间内插的FPGA-TDC,并用于时间信号量化过程中的细计数阶段。通过对系统时钟进行两次内插量化,缩短了延迟链长度,减少了延迟单元非线性在延迟链中的积累,提升了系统线性度。同时,延迟链长度的缩短使TDC中温度计码编码器等模块规模更小,降低了电路实现占用的FPGA逻辑资源。实验结果表明,该FPGA-TDC的分辨率为1.72 ps,微分非线性和积分非线性的极差分别为4.49和26.55 LSB,可实现较优的系统线性度。[Objective]Time-to-digital converters(TDCs),vital components in time measurement,have been widely used in various scientific research fields.The demand for enhanced performance in TDC resolution and improved linearity within its system has increased owing to increasingly stringent requirements across various fields.In recent years,TDCs based on field-programmable gate arrays(FPGAs)have received significant attention owing to their short development period,low cost,and improvements in FPGA fabrication processes and technology.Reducing the processing time of delay units in TDC improves TDC resolution.However,extending the length of a tapped-delay line(TDL)results in an increased nonlinear accumulation of delay units,leading to a reduction in system linearity.To address the challenge of balancing enhanced TDC resolution and preserved system linearity based on an architecture that combines coarse and fine counting,this study introduces a two-step time interpolation method designed specifically for the fine counting stage within the time signal quantization process.[Methods]In this method,the two-step time interpolation for the system clock involves the following steps.First,a set of clock signals with different phases is used to interpolate the system clock.Second,the time intervals between the adjacent phased clock signals are encapsulated using TDL.In accordance with the interpolation operation,during the time measurement process,when a start signal,triggered by a time signal,activates TDC,the first interpolation result is encoded from a one-cold code.This code is obtained using a set of synchronizers,where each synchronizer consists of two serial D flip-flops to identify the phase that corresponds to the start signal.The second interpolation result is obtained using the thermometer code encoder to process the output from TDL,which finely quantifies the time interval between the start signal and the matched phased clock signal.Finally,the quantified result of the time signal is generated by subtracting both the fir

关 键 词：时间数字转换器 现场可编程门阵列 抽头延迟链 两次时间内插 

分 类 号：TN79[电子电信—电路与系统]