一种针对TI-ADC的采样时钟相位失配数字校准技术  

A digital calibration technique for sampling clock phase mismatch for TI-ADC

作　　者：黄尚恩 施娟 蒋丽[1] 韦雪明[1] HUANG Shangen;SHI Juan;JIANG Li;WEI Xueming(Guangxi Key Laboratory of Wireless Broadband Communication and Signal Processing,Guilin University of Electronic and Technology,Guilin 541004,China)

机构地区：[1]桂林电子科技大学广西无线宽带通信与信号处理重点实验室,广西桂林541004

出　　处：《桂林电子科技大学学报》2024年第2期174-180,共7页Journal of Guilin University of Electronic Technology

基　　金：国家自然科学基金(62164003);广西无线宽带通信与信号处理重点实验室主任基金(GXKL06230106,GXKL06200131)。

摘　　要：针对采样时钟偏移失配对多相时间交织采样模数转换器(TI-ADC)性能影响很大的问题,将采样通道输出进行互相关,并利用一阶泰勒展开式进行自适应补偿校准的相位误差提取技术,有效补偿了多通道时序失配。基于65 nm CMOS工艺设计了一种12 bit 1.6 GS/s八相TI-ADC的采样相位失配校准电路。当输入信号频率为626.5625 MHz时,校准后的TIADC有效位数提升了6.29 bit,信噪失真比提升38.1 dB,无杂散动态范围提升44.44 dB。设计结果表明,本技术结构简单,硬件资源消耗少,能够显著提高TI-ADC系统采样性能。In order to solve the problem that the sampling clock offset mismatch has a great impact on the performance of multiphase time interleaved sampling analog-to-digital converter(TI-ADC),a phase error extraction technique that cross-correlates the output of the sampling channel and uses the first-order Taylor expansion for adaptive compensation calibration is proposed,which effectively compensates for the multi-channel timing mismatch.Based on the 65 nm CMOS process,a 12 bit 1.6 GS/s eight-phase TIADC sampling phase mismatch calibration circuit was designed.When the input signal frequency is 626.5625 MHz,the effective number of bits of the calibrated TI-ADC is increased by 6.29 bit,the signal-to-noise distortion ratio is increased by 38.1 dB,and the spurious-free dynamic range is increased by 44.44 dB.The design results show that the proposed technology has a simple structure and low hardware resource consumption,which can significantly improve the sampling performance of TI-ADC system.

关 键 词：TI-ADC 相位偏移失配 互相关 一阶泰勒 自适应校准 

分 类 号：TN432[电子电信—微电子学与固体电子学]