3D-SOI像素芯片逻辑层的设计与实现  

Design and Implementation of the Logic Layer for 3D-SOI Pixel Sensors

作　　者：郑炜达 周扬 卢云鹏[1,2] 徐畅 周佳 章红宇 董静[1,2] 董明义 欧阳群[1,2,3] ZHENG Weida;ZHOU Yang;LU Yunpeng;XU Chang;ZHOU Jia;ZHANG Hongyu;DONG Jing;DONG Mingyi;OUYANG Qun(Institute of High Energy Physics,CAS,Bejjing 100049,China;State Key Laboratory of Particle Detection and Electronics,Beiing 100049,China;University of Chinese Academy of Sciences,Beijing 100049,China)

机构地区：[1]中国科学院高能物理研究所,北京100049 [2]核探测与核电子学国家重点实验室,北京100049 [3]中国科学院大学,北京100049

出　　处：《核电子学与探测技术》2024年第5期791-798,共8页Nuclear Electronics & Detection Technology

基　　金：国家自然科学基金资助,项目批准号11935019,11575220。

摘　　要：环形正负电子对撞机(CEPC)实验对顶点探测器的空间分辨率提出了极为苛刻的要求。SOI像素传感器芯片CPV-4使用了3D堆叠技术来满足CEPC需要的高空间分辨率。本文主要研究在3DSOI技术下CPV-4的逻辑层电路设计与验证。逻辑层作为CPV-43D芯片的上层部分包含粒子击中信息的存储和读出功能,采用了紧凑的像素逻辑设计和高效的优先级编码读出逻辑设计。测试系统基于IPBUS协议实现了逻辑交互、数据传输和用户界面的软硬件功能,同时开发了模仿逻辑层功能和接口的仿真器模块。通过对仿真器模块、单独的上层芯片以及3D堆叠后的片上逻辑层进行对比测试,完整验证了片上逻辑层的电路功能,并证明了3D堆叠的键合、减薄和顶层金属化等工艺步骤对片上逻辑层没有不利影响。3D-SOI像素芯片的逻辑电路设计和3D堆叠技术研发取得了初步进展。The circular electron positron collider(CEPC)experiment poses extremely demanding requirements on the spatial resolution of the vertex detector.The prototype chip of SOI pixel sensor CPV-4 employs 3D-SOI technology to meet the high spatial resolution needed for CEPC.This work primarily investigates the logic layer circuit design and verification under 3D-SOI technology for CPV-4.The logic layer,as the upper part of the CPV-43D chip,includes the storage and readout functions for particle hit information,utilizing a compact pixel logic design and an efficient priority encoding readout logic design.The test system implements logic interaction,data transmission,and user interface software and hardware functions based on the IPBUS protocol.Meanwhile we also developed an emulator module that mimics the logic layer's functionality and interface.Through comparative testing of the emulator module,the individual upper-tier chip,and the upper-tier logic layer after 3D integration,the upper-tier logic layer's circuit functionality is fully verified,demonstrating that 3D integration processes such as bonding pad,thinning,and top metallization do not adversely affect the on-chip logic layer.Preliminary progress has been made in the design of the logic circuit for the 3D-SOI pixel chip and the development of 3D integration technology.

关 键 词：CEPC 顶点探测器 3D-SOI 芯片测试 

分 类 号：TN47[电子电信—微电子学与固体电子学]