基于Farrow架构的任意倍重采样的FPGA设计与实现  

Design and Implementation of Arbitrary Multiple Resampling FPGA Based on Farrow Architecture

作　　者：袁明 胡志臣 张延顺[1] 武福存[2] 朱硕鹏 蒋明明 YUAN Ming;HU Zhichen;ZHANG Yanshun;WU Fucun;ZHU Shuopeng;JIANG Mingming(School of Instrumentation Science and Opto-Electronics Engineering,Beihang University,Beijing 100191,China;Beijing Aerospace Measurement&Control Technology Co.,Ltd.,Beijing 100041,China)

机构地区：[1]北京航空航天大学仪器科学与光电工程学院,北京100191 [2]北京航天测控技术有限公司,北京100041

出　　处：《计算机测量与控制》2024年第10期263-268,276,共7页Computer Measurement &Control

摘　　要：任意波形发生器通常使用直接数字波形合成技术生成任意波形,然而使用此技术实现可变采样率功能时,需要调整时钟的工作频率,导致输出中存在难以滤除的镜像频率以及硬件实现难度增加;针对上述问题,对基于Farrow架构的任意倍重采样方法进行了研究,在FPGA上进行了固定时钟驱动下的32路并行的任意倍重采样的逻辑设计与实现;并针对逻辑实现中出现的量化误差积累问题,提出了清除累积误差的逻辑实现方案;经实验测试,实现了在187.5 MHz固定时钟驱动下1 ksps~6 Gsps范围的采样率转换,并解决了量化误差积累造成的长时间运行时波形失真的问题。Arbitrary waveform generators usually employ direct digital waveform synthesis techniques to generate arbitrary waveform.However,when this technology is used to achieve a variable sampling rate,it needs to adjust the working frequency of the clock,resulting in image frequencies that are difficult to filter out in the output and increasing the complexity of hardware implementation.To address these issues,research is conducted on an arbitrary multiple resampling method based on the Farrow architecture.A parallel implementation of a 32-channel arbitrary resampling system is designed and realized on an FPGA under a fixed clock drive.Additionally,a logical implementation scheme for clearing error accumulation is proposed to accumulate quantization errors in logical implementation.Experimental results demonstrate that the system achieves sampling rate conversion from 1 ksps to 6 Gsps with a fixed clock frequency of 187.5 MHz and effectively solves waveform distortion caused by quantization error accumulation during long-term operation.

关 键 词：采样率 Farrow架构 并行 任意倍重采样 量化误差 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]