Energy-Efficient Dynamic Configurable Datapath Architecture for IoT Devices  

作　　者：Ruizhe Zhang Junhui Liu Han Wang Li Lu 

机构地区：[1]Laboratory of Intelligent Collaborative Computing,University of Electronic Science and Technology of China,Chengdu 611731,China [2]School of Computer Science and Engineering,University of Electronic Science and Technology of China,Chengdu 611731,China

出　　处：《Journal of Communications and Information Networks》2024年第3期251-261,共11页通信与信息网络学报（英文）

基　　金：supported by the National Natural Science Foundation of China under Grant U21A20462.

摘　　要：This paper introduces a novel RISC-V processor architecture designed for ultra-low-power and energy-efficient applications,particularly for Internet of things(IoT)devices.The architecture enables runtime dynamic reconfiguration of the datapath,allowing efficient balancing between computational performance and power consumption.This is achieved through interchangeable components and clock gating mechanisms,which help the processor adapt to varying workloads.A prototype of the architecture was implemented on a Xilinx Artix 7 field programmable gate array(FPGA).Experimental results show significant improvements in power efficiency and performance.The mini configuration achieves an impressive reduction in power consumption,using only 36%of the baseline power.Meanwhile,the full configuration boosts performance by 8%over the baseline.The flexible and adaptable nature of this architecture makes it highly suitable for a wide range of low-power IoT applications,providing an effective solution to meet the growing demands for energy efficiency in modern IoT devices.

关 键 词：dynamic reconfiguration Internet of things(IoT) power efficiency RISC-V 

分 类 号：TP391.44[自动化与计算机技术—计算机应用技术]