面向FT-M7002平台拉普拉斯算法的优化实现  

OPTIMIZED REALIZATION OF LAPLACIAN ALGORITHM FOR FT-M7002

作　　者：郭子涵 范明亮 李靖[1] 商建东 Guo Zihan;Fan Mingliang;Li Jing;Shang Jiandong(Zhengzhou University,Zhengzhou 450000,Henan,China;National Supercomputing Center in Zhengzhou,Zhengzhou 450000,Henan,China)

机构地区：[1]郑州大学,河南郑州450000 [2]国家超级计算郑州中心,河南郑州450000

出　　处：《计算机应用与软件》2024年第10期276-281,361,共7页Computer Applications and Software

基　　金：国家重点研发计划项目(X0008606);郑州大学2018年科研启动基金项目(32210919)。

摘　　要：为了充分发挥国产FT高性能处理器的平台优势,针对其对拉普拉斯算法进行并行优化,在数据迁移的基础上使用DMA数据传输机制解决数组矩阵转置、数据访问不连续以及数据传输存在时间间隙的问题,提高了程序性能,充分发掘了程序的数据级和指令级并行性。实验结果表明,优化后的向量化并行算法较优化前,获得了2.02~2.55倍的加速效果。相较于TMS320C6678处理器,FT优化之后的算法可达到其1.48~2.56倍的效果。In order to give full play to the platform advantages of domestic FT high-performance processor,we optimize the Laplace algorithm in parallel for it.On the basis of data moving,DMA data transfer mechanism was used to solve the problems of array matrix transpose,data access discontinuity and data transfer time gap,so as to improve the performance of the program and fully explore the data level and instruction level parallelism of the program.The experimental results show that the optimized vectorization parallel algorithm achieves 2.02~2.55 times faster acceleration than before.Compared with TMS320C6678 processor,the efficiency of FT optimized algorithm can reach 1.48~2.56 times.

关 键 词：高性能处理器 拉普拉斯算法 并行优化 DMA数据传输 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]