基于Verilog HDL的SM3算法硬件架构仿真设计  

Design and simulation of SM3 algorithm hardware architecture based on Verilog hardware description language

作　　者：方硕 姜博 王立晶 刘云涛[1] 邵雷[1] FANG Shuo;JIANG Bo;WANG Lijing;LIU Yuntao;SHAO Lei(Key Laboratory of Advanced Marine Communication and Information Technology Ministry of Industry and Information Technology,College of Information and Communication Engineering,Harbin Engineering University,Harbin 150001,China)

机构地区：[1]哈尔滨工程大学信息与通信工程学院,先进船舶通信与信息技术工信部重点实验室,黑龙江哈尔滨150001

出　　处：《实验技术与管理》2024年第10期35-42,共8页Experimental Technology and Management

基　　金：国家自然科学基金项目(62104054)。

摘　　要：哈希函数由于其不可逆与碰撞约束的特点,可以很好地完成对信息的加密,但算法硬件吞吐率有待提高。该研究首先根据SM3杂凑密码哈希算法,结合Merkle-Damgard结构深入研究密码杂凑原理,分析得出硬件实现方案;其次结合静态时序分析,针对关键路径进行分析,优化得到最终硬件电路实现方案;最后利用CSA结构优化加法器结构,采用二合一结构以提高算法硬件的吞吐率。使用Stratix II芯片通过Modelsim进行仿真,在Quartus平台下完成FPGA的功能验证。经过功能验证、时序分析、逻辑综合、时序验证后,计算出最高吞吐率可达到1.07 Gb/s。实现了较高吞吐率,以及面积与速度的相对平衡。[Objective]With the rapid development of the Internet of Things and network communication technology,cryptography has advanced significantly.Current hash function software can process multiple messages in parallel,making hash functions widely applicable for file tamper-proofing and software installation verification on mobile phones.However,existing hash function software often suffers from low speed and throughput,which hinders the processing of large-scale data in Internet of Things applications.Algorithm hardware can efficiently process large-scale data through algorithm adaptation and path optimization.Consequently,this experiment designs a hardware circuit for the SM3 cryptographic hash algorithm using Verilog hardware description language(HDL)to enhance the speed and throughput of the algorithm,thereby addressing the demand for high-speed hashing algorithms in Internet of Things applications.[Methods]This paper examines the speed and throughput of hash algorithm hardware using various optimization technologies and loop expansion methods.By comparing different techniques,the experiment presents an optimized SM3 hash algorithm.The Verilog HDL code implements the hardware circuit for the SM3 cryptographic hash algorithm,which is simulated using ModelSim by Mentor Graphics Corporation.According to the simulation results from the static sequence,the experiment identifies the critical path of the hardware.Leveraging this static sequence analysis,the study employs loop expansion technology and the conditional-select adder(CSA)to enhance processing speed and shorten the critical path.Furthermore,the FPGA is used to implement the hardware system experimentally and conduct a sequence test to evaluate throughput.According to the experimental results,the hardware incorporates the two-in-one structure loop expansion technology,which reduces two-step calculations to one step.As a result,the number of iterations for compression decreases from 64 to 32.This structure significantly improves calculation efficiency and reduce

关 键 词：杂凑算法 SM3 硬件实现 FPGA 高吞吐率 

分 类 号：P235.1[天文地球—摄影测量与遥感]