一种适用于亚采样锁相环的高鲁棒性辅助锁定电路  

A Robust Lock Aided Circuit for Sub-Sampling Phase-Locked Loop

作　　者：张磊[1] 林敏[1] Zhang Lei

机构地区：[1]上海大学特种光纤与光接入网重点实验室,上海200444

出　　处：《工业控制计算机》2024年第10期124-125,128,共3页Industrial Control Computer

摘　　要：当前的研究表明,基于亚采样相位检测器(Sub-Sampling Phase Detectors,SSPD)的锁相环(Phase-Locked Loop,PLL)相较传统锁相环架构可以实现显著降低的带内相位噪声。然而,在片上系统(Systems on Chip,SOCs)应用中,PLL容易受到衬底或电源耦合的干扰,这很可能会导致PLL失去锁定,且可能无法恢复。针对此问题,提出一种将辅助锁频环(Frequency-Locked Loop,FLL)和数字锁定检测器(Digital Lock Detector,DLD)相结合的适用于亚采样锁相环(Sub-Sampling Phase-Locked Loop,SSPLL)的高鲁棒性辅助锁定电路。仿真结果表明:与传统SSPLL相比,所提出的电路极大提升了PLL对衬底或电源干扰的鲁棒性,同时保持了其低相位噪声的优点,这对于SSPLL在大规模生产和应用中的可靠性具有重要意义。Current research demonstrates that phase-locked loop(PLL)based on sub-sampling phase detector(SSPD)can achieve much lower in-band phase noise.However,in systems on chip(SOCs)application,PLLs are susceptible to interference from substrate or power supply coupling,which may cause the PLLs unlock and potentially unable to recover.To address this issue,this paper proposes a robust lock aided circuit for sub-sampling phase-locked loop(SSPLL)that combines a frequency-locked loop(FLL)and a digital lock detector(DLD).Simulation results indicate that the proposed circuit greatly improves PLL-robustness to substrate or power supply interference compared to traditional SSPLL while maintaining its low phase noise merit,which is of significance for SSPLL reliability in mass production and application.

关 键 词：亚采样相位检测器 锁频环 数字锁定检测器 锁相环 

分 类 号：TN710[电子电信—电路与系统]