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作 者:谭会生[1] 卿翔 肖鑫凯 Tan Huisheng;Qing Xiang;Xiao Xinkai(College of Railway Transportation,Hunan University of Technology,Zhuzhou 412000,China)
机构地区:[1]湖南工业大学轨道交通学院,湖南株洲412000
出 处:《半导体技术》2024年第11期988-997,共10页Semiconductor Technology
基 金:湖南省教育厅科学研究重点项目(20A163);湖南省学位与研究生教学改革研究项目(2022JGYB183)。
摘 要:为了提升永磁直线同步电机(PMLSM)电流控制的稳态性能和执行速度,同时降低资源消耗,基于现场可编程门阵列(FPGA)设计了一个三矢量模型预测电流控制(TV-MPCC)知识产权(IP)核,并利用FPGA在环可视化验证方法,建立了一个PMLSM的TV-MPCC IP核验证系统。通过Simulink对TV-MPCC策略进行算法级仿真,并优化了基本电压矢量的作用顺序;采用并行与资源共享硬件优化技术设计并封装了一个TV-MPCC IP核,并对其进行了功能仿真;将设计部署在FPGA芯片XC7Z020CLG400-2上,利用FPGA在环可视化验证平台进行实验研究。结果表明,TV-MPCC策略下d、q轴电流跟踪误差和电流脉动均降低90%以上;FPGA工作在100 MHz下,实现一次算法的时间为0.62μs,仅为软件PyCharm执行时间的0.414%。To enhance the steady-state performance and execution speed of the current control for a permanent magnet linear synchronous motor(PMLSM)while reducing resource consumption,a threevector model predictive current control(TV-MPCC)intellectual property(IP)core was designed based on a field programmable gate array(FPGA).With the FPGA-in-the-loop visual verification method,a verification system for the TV-MPCC IP core of PMLSM was established.The TV-MPCC strategy was simulated at the algorithm level using Simulink,and the action order of basic voltage vectors was optimized.A TV-MPCC IP core was designed and encapsulated with hardware optimization techniques such as parallelism and resource sharing,and the functional simulation of which was performed.The design was deployed on the FPGA chip XC7Z020CLG400-2,and experimental research was conducted on the FPGA-in-the-loop visual verification platform.The results show that under the TV-MPCC strategy,the d-and q-axis current tracking errors and current ripples are reduced by more than 90%.The FPGA,operating at 100 MHz,achieves an execution time of 0.62μs per iteration of the algorithm,which is only 0.414%of the execution time in the software PyCharm.
关 键 词:永磁直线同步电机(PMLSM) 三矢量模型预测电流控制(TV-MPCC) 现场可编程门阵列(FPGA) 电流跟踪误差 电流脉动
分 类 号:TN43[电子电信—微电子学与固体电子学]
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