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作 者:宁继超 贲洪奇[1] 王雪松 孟涛[3] Ning Jichao;Ben Hongqi;Wang Xuesong;Meng Tao(School of Electrical Engineering and Automation,Harbin Institute of Technology,Harbin 150001,China;State Grid Harbin Power Supply Company,Harbin 150000,China;School of Mechanical and Electrical Engineering,Heilongjiang University,Harbin 150080,China)
机构地区:[1]哈尔滨工业大学电气工程及自动化学院,哈尔滨150001 [2]国网哈尔滨供电公司,哈尔滨150000 [3]黑龙江大学机电工程学院,哈尔滨150080
出 处:《电工技术学报》2024年第20期6444-6461,共18页Transactions of China Electrotechnical Society
摘 要:针对二极管钳位型三电平逆变器存在的电容电压平衡问题和死区时间导致的输出波形失真问题,该文在分析死区时间对输出波形失真及电容电压平衡影响的基础上,提出一种可用于高频逆变器的数字调制方法及具体实现形式,分析量化与采样环节、数字隔离器件传输延时及采样时钟对所提方法的影响,并给出开关时钟分频倍数的设计准则。该方法独立于闭环控制系统其他环节,无需电流采样,实现容易且易于集成在数字控制器中;无需控制环路运算,可适用于更高开关频率和输出频率。仿真和实验表明,所提方法在不同开关频率、不同死区时间和不同负载类型下均能有效地降低死区时间导致的输出波形失真现象,且能够很好地解决电容电压平衡问题。此外,所提方法在开关频率高达400 kHz的情况下仍具有良好的效果。With the development of wide bandgap semiconductor devices,high power density can be achieved by high switching frequencies combined with diode-clamped three-level inverters(DCTLI)and wide bandgap semiconductor devices like gallium nitride(GaN)and silicon carbide(SiC).However,problems that are well solved at low switching frequencies may be difficult to solve at high switching frequencies.In DCTLI,there are two main problems:the influence of dead time and the capacitor voltage balance.Dead time introduces harmonics into the output waveform,degrading the output waveform quality.Unbalanced capacitor voltages reduce converter reliability and even damage transistors.In addition,delay mismatches associated with dead time affect capacitor voltage balance.However,limited by computing power requirements,existing methods are challenging to achieve good results at high switching frequencies,and the additional sensors required are not conducive to realizing high power density.Therefore,the effects of dead time on the output waveform and capacitor voltage balance are analyzed.Then,a digital modulation method without additional sensors is proposed for high switching frequencies.The resistor divider network introduces the output voltage information of the bridge.The driving signal is generated by making the count value of the output voltage of the bridge equal to the reference signal.Accordingly,the average value of the inverter bridge output waveform is forced to track the reference signal,so dead time effects are compensated directly in the modulator section.The capacitor voltage balance state is collected through the resistor voltage dividing network,and the balance state is accumulated through the counter.As a result,the modulator obtains the degree of capacitor voltage imbalance and modifies the reference signal to balance the capacitor voltage.In addition,the effects of the quantization and sampling,the propagation delay of the digital isolator,and the finite sampling clock on the proposed method are analyzed.It is shown
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