基于全自旋逻辑器件的五输入择少逻辑门设计  

Proposal of a Five⁃input Minority Gate Based on All⁃spin Logic Device

作　　者：王森 李鹤楠 WANG Sen;LI Henan(School of Intelligence and Electronic Engineering,Dalian Neusoft University of Information,Dalian,Liaoning,116023,CHN)

机构地区：[1]大连东软信息学院智能与电子工程学院,辽宁大连116023

出　　处：《固体电子学研究与进展》2024年第4期331-336,共6页Research & Progress of SSE

摘　　要：基于全自旋逻辑器件提出了一种五输入择少逻辑门,并基于Landau-Lifshitz-Gilbert-Slonczewski方程和自旋传输模型,建立了择少逻辑门的自一致仿真模型。基于该自一致仿真模型验证了所提出的逻辑门的功能正确性。同时,研究了五输入择少逻辑门的功耗和延迟问题,发现其功耗不随输入的改变而改变,平均功耗约为1.174 pJ,但延迟时间随输入的不同而变化,最大延迟约为1.9 ns。相对于三输入择少逻辑门,所提出的五输入择少逻辑门在构造译码器、编码器、奇偶校验器等较为复杂的逻辑电路时,在器件数量和时钟周期上都有所减少。A five-input minority gate based on all-spin logic device(ASLD)was proposed,and a self-consistent simulation model for the minority gate was established based on the Landau-Lifshitz-Gilbert-Slonczewski equation and spin transfer model.The self-consistent model was employed to demonstrate the validity of the five-input minority gate and analyze its energy dissipation and delay issues.It is found that the energy dissipation does not vary with the input of minority gate,with an average energy dissipation of approximately 1.174 pJ.But the delay time varies with input,with a maximum delay of approximately 1.9 ns.Compared to the three-input minority gate,the pro-posed five-input minority gate reduces the number of devices and clock cycles when constructing com-plex logic circuits such as decoders,encoders,and parity checkers.

关 键 词：全自旋逻辑 自旋传输 Landau-Lifshitz-Gilbert-Slonczewski方程 择少逻辑门 

分 类 号：TN791[电子电信—电路与系统] TN389