高速背板的设计及测试研究  

Research into the Design and Test of High Speed Backplane of 25 Gb/s

作　　者：魏东明 张靓 WEI Dongming;ZHANG Liang(The 723 Institute of CSSC,Yangzhou 225101,China;Northern Naval Security Department,Qingdao 266000,China)

机构地区：[1]中国船舶集团有限公司第七二三研究所,江苏扬州225101 [2]北部战区海军保障部,山东青岛266000

出　　处：《舰船电子对抗》2024年第5期83-89,共7页Shipboard Electronic Countermeasure

摘　　要：高速背板作为高速串行链路的重要组成部分,随着高速背板连接器的蓬勃发展和日益提升的速率需求而不断迭代。从高速背板性能指标约束、设计流程和信号完整性验证3个方面,总结25 Gbps高速背板的信号完整性保证的控制方法及相关测试指导,为高速背板的设计提供参考。As an important part of high-speed serial link,the high speed backplane has been iterated continuously with the vigorous development of high-speed backplane connectors and the increasing demand for speed.This paper summarizes the control methods of signal integrity assurance of highspeed backplane of 25 Gb/s from three aspects:performance constraints,design process and signal integrity verification,which provides reference for the design of high-speed backplane.

关 键 词：高速串行链路 25 Gb/s高速背板 信号完整性 

分 类 号：TM503[电气工程—电器]