一种可重构异构内存架构和控制器  

A Reconfigurable Heterogeneous Memory Architecture and Memory Controller

作　　者：靳晓忠 刘海坤 赖皓[1,2] 毛伏兵 张宇 廖小飞[1,2] 金海[1,2] JIN Xiao-zhong;LIU Hai-kun;LAI Hao;MAO Fu-bing;ZHANG Yu;LIAO Xiao-fei;JIN Hai(National Engineering Research Center for Big Data Technology and System/Services Computing Technology and System Lab/Cluster and Grid Computing Lab,Huazhong University of Science and Technology,Wuhan,Hubei 430074,China;School of Computing Science and Technology,Huazhong University of Science and Technology,Wuhan,Hubei 430074,China)

机构地区：[1]大数据技术与系统国家地方联合工程研究中心/服务计算与系统教育部重点实验室/集群与网格计算湖北省重点实验室,华中科技大学,湖北武汉430074 [2]华中科技大学计算机科学与技术学院,湖北武汉430074

出　　处：《电子学报》2024年第9期3038-3051,共14页Acta Electronica Sinica

基　　金：国家自然科学基金(No.62072198);湖北省自然科学基金(No.2021CFA037)。

摘　　要：融合传统动态随机访问存储器(Dynamic Random Access Memory,DRAM)与新型非易失性内存(NonVolatile Memory,NVM)可构建平行架构或层次架构的异构内存系统.平行架构的异构内存系统往往需要通过页迁移技术把热点数据从NVM迁移到DRAM以提高访存性能,然而在操作系统中实现热页监测和迁移会带来巨大的软件性能开销.硬件实现的层次架构由于增加了访存层次,对于访存局部性差的大数据应用反而增加了访存延迟.为此,本文提出可重构的异构内存架构,可以运行时在平行和层次架构间进行转换以动态适配不同应用的访存特性.设计了基于新型指令集架构RISC-V(Reduced Instruction Set Computing-V)的DRAM/NVM异构内存控制器,利用少量硬件计数器实现了访存踪迹统计和分析,并实现了DRAM和NVM物理页间的动态映射和高效迁移机制.实验表明,DRAM/NVM异构内存控制器可提高43%的应用性能.Heterogeneous memory systems composed of traditional dynamic random access memory(DRAM)and new non-volatile memory(NVM)can be organized in a horizontal architecture or a hierarchical architecture.The horizontal DRAM/NVM architecture often requires page migration technologies to improve memory access performance.However,hot page monitoring and migration implemented in operating systems would cause significant software performance over⁃head.The hardware-supported hierarchical architecture even increases the memory access latency for big data applications with poor data locality due to the deeper memory hierarchy.To this end,this paper proposes a reconfigurable heterogeneous memory architecture that can be converted between horizontal and hierarchical architectures at runtime to dynamically adapt the memory access characteristics of different applications.We design a DRAM/NVM heterogeneous memory con⁃troller(HMC)based on the new instruction set architecture RISC-V(Reduced Instruction Set Computing-V).The HMC us⁃es a few hardware counters for memory access monitoring and analyzing,and achieves dynamic address mapping and eff icient page migration between DRAM and NVM pages.Experimental results show that the DRAM/NVM hybrid memory controller can improve application performance by 43%.

关 键 词：非易失性内存 异构内存系统 异构内存控制器 内存访问监测 页迁移 

分 类 号：TP32[自动化与计算机技术—计算机系统结构]