数字音频传输中的低抖动锁相环设计  

Design of Low Jitter Phase-locked Loop in Digital Audio Transmission

作　　者：殷弼君 时婷婷 邹勤丽 YIN Bijun;SHI Tingting;ZHOU Qinli(CETC 32nd Research Institute,Shanghai 201804,China)

机构地区：[1]中国电子科技集团公司第三十二研究所,上海201804

出　　处：《电子技术（上海）》2024年第8期13-15,共3页Electronic Technology

摘　　要：阐述采用国内0.18μm工艺,设计并实现一个低抖动锁相环。提出一种三阶低通采样滤波器结构对相位噪声进行优化。锁相环功耗在锁定状态下为60mW,输出时钟频率44.1kHz,抖动为5ps,10kHz频偏下相位噪声为97.61dB/Hz。This paper describes domestic 0.18μm technology to design and implement a low jitter phase-locked loop,and proposes a structure of a third-order low-pass sampling filter to optimize phase noise.The power consumption of the phase-locked loop is 60mW in the locked state,and the phase noise is 97.61dB/Hz under a frequency offset of 10kHz.

关 键 词：数字音频 锁相环 低通滤波器 抖动 相位噪声 

分 类 号：TN713[电子电信—电路与系统] TN911.8