基础三维无源元件的单片高集成度自卷曲技术  

Monolithic Highly Integrated Self-Rolled up Membrane Nanotechnology for Basic 3D Passive Components

作　　者：黄文 桑磊 黄高山[2] 顾昌展 张勇[4] 沈瞿欢 毕秀文 HUANG Wen;SANG Lei;HUANG Gaoshan;GU Changzhan;ZHANG Yong;SHEN Quhuan;Bi Xiuwen(School of Microelectronics,Hefei University of Technology,Hefei 230009;Department of Materials Science,Fudan University,Shanghai 200433;Department of electrical engineering,Shanghai Jiao Tong University,Shanghai 200030;School of Electronic Science and Engineering,University of Electronic Science and Technology of China,Chengdu 611731;Tiantong Ruihong Technology Co.,Ltd.,Jiaxing 314000)

机构地区：[1]合肥工业大学微电子学院,合肥230009 [2]复旦大学材料科学系,上海每200433 [3]上海交通大学电子工程系,上海200030 [4]电子科技大学电子科学与工程学院,成都611731 [5]天通瑞宏科技有限公司,嘉兴314000

出　　处：《中国基础科学》2024年第4期17-24,共8页China Basic Science

基　　金：国家重点研发计划项目(2021YFA0715300)。

摘　　要：在射频前端芯片中,无源元件占据大量面积,这成为芯片小型化的瓶颈。为了应对这一挑战,介绍一种基于传统平面半导体工艺的单片自卷曲技术。该技术利用薄膜应力实现了基础无源元件对三维空间的充分利用,从而显著减少了基础无源元件在芯片中所占的面积,相比传统的二维平面器件更具优势。通过全面介绍这一技术的原理、表征以及集成应用等,展示了其在推动射频前端芯片向高集成度和小型化方向发展的潜力。In radio frequency(RF)front-end chips,passive components often occupy a large area,which becomes a bottleneck for miniaturization.To address this challenge,this paper introduces a monolithic self-rolled up membrane(S-RuM)nanotechnology based on conventional planar semiconductor processes.This technology leverages multilayers stress to fully utilize three-dimensional(3D)space,significantly reducing the on-chip footprint of basic passive components on chip compared to traditional two-dimensional(2D)planar devices.This paper comprehensively covers the principle,characterization,and integration applications of this technology,demonstrating its potential in promoting the development of RF front-end chips towards higher integration and miniaturization.

关 键 词：自卷曲技术 射频前端芯片 基础三维无源元件 高集成度和小型化 

分 类 号：TM501[电气工程—电器]