面向高性能计算机光互连的低抖动Retimer电路  

A low-jitter Retimer circuit for high-performance computer optical interconnection

作　　者：刘庆 王和明[1] 吕方旭 张庚 吕栋斌 LIU Qing;WANG He-ming;L Fang-xu;ZHANG Geng;L Dong-bin(Air and Missile Defense College,Air Force Engineering University,Xi’an 710051;College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;Troop 66029 of PLA,Xilin Gol League 011213,China)

机构地区：[1]空军工程大学防空反导学院,陕西西安710051 [2]国防科技大学计算机学院,湖南长沙410073 [3]中国人民解放军66029部队,内蒙古锡林郭勒盟011213

出　　处：《计算机工程与科学》2024年第11期1940-1948,共9页Computer Engineering & Science

基　　金：国家自然科学基金(62204263)。

摘　　要：随着通信带宽的大幅提升,低抖动作为多场景应用中信号传输质量的关键指标,已成为信号完整性研究的重要方向。56 Gbaud的Retimer芯片是高性能计算机光互连数据传输的关键核心芯片,其抖动性能也制约着光模块高性能计算机的整体性能。针对传统高速Retimer芯片抖动性能低的难题,首次提出了数据速率超过100 Gbps的低抖动Retimer电路。Retimer电路基于CDR+PLL架构,集成在光纤中继器中,具有均衡和全速率重定时功能;采用抖动消除的滤波电路,能在高噪声输入信号下取得良好的输出数据抖动性能,为解决传统Retimer直接采样转发导致输出数据抖动大的问题提供了技术支持。采用TSMC 28 nm CMOS工艺完成了基于CDR+PLL架构的低抖动Retimer电路设计。仿真结果表明,当输入112 Gbps PAM4时,Retimer的输出数据抖动为741 fs,相比于传统Retimer结构降低了31.4%。With the significant increase in communication bandwidth,low jitter,as a crucial indicator of signal transmission quality in multi-scenario applications,has become an important research direction in signal integrity.The 56 Gbaud Retimer chip serves as the key component in optical interconnection data transmission for high-performance computers,and its jitter performance also restricts the overall performance of the optical module in high-performance computers.To address the challenge of low jitter performance in traditional high-speed Retimer chips,a low-jitter Retimer circuit with a data rate exce-eding 100 Gbps is proposed for the first time.This Retimer circuit,based on the CDR+PLL architecture,is integrated into a fiber optic repeater,featuring equalization and full-rate retiming functions.By adopting a jitter elimination filter circuit,it achieves excellent output data jitter performance under high-noise input signals,providing technical support for solving the issue of high output data jitter caused by direct sampling and forwarding in traditional Retimers.The design of the low-jitter Retimer circuit based on the CDR+PLL architecture was completed using TSMC 28 nm CMOS technology.Simulation results show that when the input is 112 Gbps PAM4,the output data jitter of the Retimer is 741 fs,representing a 31.4%reduction compared to traditional Retimer structures.

关 键 词：Retimer电路 时钟数据恢复(CDR) 锁相环(PLL) 低抖动 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]