一种高性能、小面积的Sigma Delta DAC数字电路设计  

作　　者：白创 赵军武 

机构地区：[1]长沙理工大学物理与电子科学学院,长沙410114

出　　处：《科技创新与应用》2024年第33期107-110,114,共5页Technology Innovation and Application

基　　金：湖南省教育厅科研项目-优秀青年项目(22B0287)。

摘　　要：该文设计一种高性能、小面积的Sigma Delta DAC,其中包括插值滤波器和数字调制器。插值滤波器由两级半带滤波器和CIC滤波器级联组成,实现128倍插值。在两级半带滤波器硬件实现中,滤波器系数采用查找表实现,滤波运算数据采用SRAM存储,并通过乘法器的时分复用实现,大大减少对硬件资源的使用。数字调制器采用量化误差反馈型的多bit量化Mash 1-1-1结构,这种结构不需要复杂的乘法运算,简化设计并提高系统的可靠性。该DAC数字电路在90 nm CMOS工艺下实现,面积为0.0535 mm^(2),功耗为1.0103 mW。经过测试,数字调制器输出的带内信噪比为132.2 dB,有效位数21.67,可以满足小面积、高性能DAC的设计需求。This paper presents a high-performance,small-footprint Sigma Delta DAC,which includes an interpolation filter and a digital modulator.The interpolation filter consists of two-stage half-band filters cascaded with a CIC filter,achieving 128x interpolation.In the hardware implementation of the two-stage half-band filters,the filter coefficients are implemented using lookup tables,while the filter operation data is stored in SRAM and implemented through multiplexer-based time-sharing,significantly reducing hardware resource utilization.The digital modulator adopts a quantization error feedback-based multi-bit quantization MASH 1-1-1 structure,which eliminates the need for complex multiplication operations,simplifying the design and enhancing system reliability.Implemented in a 90 nm CMOS process,the digital circuit occupies an area of 0.0535 mm^(2) and consumes 1.0103 mW.Test results show that the digital modulator achieves an in-band signal-to-noise ratio of 132.2 dB with an effective number of bits of 21.67,meeting the requirements for designing small-footprint,high-performance DACs.

关 键 词：Sigma Delta DAC 小面积 插值滤波器 芯片 

分 类 号：TN761[电子电信—电路与系统]