一种应用于物联网的高精度SAR ADC  

A high-precision SAR ADC applied to the internet of things

作　　者：翁烜非 魏聪 周圻坤 王仁平[1] 魏榕山[1] WENG Xuanfei;WEI Cong;ZHOU Qikun;WANG Renping;WEI Rongshan(College of Physic and Information Engineering,Fuzhou University,Fuzhou 350116,China)

机构地区：[1]福州大学物理与信息工程学院,福建福州350116

出　　处：《微电子学与计算机》2024年第11期60-67,共8页Microelectronics & Computer

基　　金：国家自然科学基金(92064006);福建省自然科学基金(2023J01398)。

摘　　要：基于180 nm CMOS工艺,设计了一种应用于物联网的14-bit逐次逼近型模数转换器(Successive Approximation Analog-to-Digital Converter,SAR ADC)。电容阵列采用分段和冗余技术,高段电容加入了两位冗余电容,在提高ADC的精度与线性度的同时也减少了版图面积。为了实现高精度,采用了一种基于电荷泵的失调电压降低技术的动态比较器,基于电荷泵的逐次逼近比较环路改变全动态预放大器两个输入晶体管的衬底电压差值,有效的补偿了失调电压,最终稳定在一个小的失调步长内。相比于传统静态预放大器,全动态预放大器节省了更多的功耗,相比于现有电荷泵补偿技术,使用更加简单的校准逻辑,大大减少数字电路的开销。动态器件匹配(DEM)技术用于提高电容阵列最高3位的电容的匹配度,将最高3位的电容拆分为大小相等的7个电容,让电容转换过程中,被选中的概率相同,将电容失配的误差平均化,从而将谐波平均分布到频域范围,以减少电容失配的影响。仿真结果表明,在采样频率为4 kS/s时,供电电压为1.8 V的条件下,无杂散动态范围为94.9 dB,功耗为1.002μW,有效位数为13.01 bit。A 14-bit successive approximation Analog-to-Digital converter(SAR ADC)for Internet of Things(IoT)applications,designed using the 180 nm CMOS process,is introduced.The capacitor array employs segmentation and redundancy techniques,adding two redundant capacitors in the high-segment capacitor,which improves the accuracy and linearity of the ADC while reducing the layout area.To achieve high precision,a dynamic comparator using a charge pumpbased offset voltage reduction technique is implemented.The successive approximation comparison loop based on the charge pump alters the substrate voltage difference of the two input transistors of the fully dynamic preamplifier,effectively compensating for the offset voltage and ultimately stabilizing within a small offset step.Compared to a traditional static preamplifier,the fully dynamic preamplifier saves more power consumption.Compared to existing charge pump compensation techniques,it uses simpler calibration logic,significantly reducing the cost of digital circuits.Dynamic Element Matching(DEM)technology is used to improve the matching of the top three bits of capacitance in the capacitor array.The top three bits of capacitance are split into seven equal-sized capacitors,allowing for equal probability of selection during the capacitance conversion process.This averages out the error due to capacitor mismatch,thereby distributing the harmonics evenly across the frequency domain to minimize the impact of capacitor mismatch.Simulation results show that at a sampling frequency of 4 kS/s and a supply voltage of 1.8 V,the Spurious-Free Dynamic Range(SFDR)is 94.9 dB,power consumption is 1.002μW,and the ENOB of bits is 13.01 bit.

关 键 词：物联网 逐次逼近型模数转换器 高精度比较器 分段电容阵列 低功耗 

分 类 号：TN792[电子电信—电路与系统]