Tailoring lithium intercalation pathway in 2D van der Waals heterostructure for high-speed edge-contacted floating-gate transistor and artificial synapses  

作　　者：Jun Yu Jiawei Fu Hongcheng Ruan Han Wang Yimeng Yu Jinpeng Wang Yuhui He Jinsong Wu Fuwei Zhuge Ying Ma Tianyou Zhai 

机构地区：[1]State Key Laboratory of Materials Processing and Die and Mould Technology,School of Material Science and Engineering,Huazhong University of Science and Technology(HUST),Wuhan,the People's Republic of China [2]Hubei Yangtze Memory Laboratory,School of Integrated Circuits,Huazhong University of Science and Technology(HUST),Wuhan,the People's Republic of China [3]School of Information Engineering,Zhongnan University of Economics and Law,Wuhan,the People's Republic of China [4]State Key Laboratory of Advanced Technology for Materials Synthesis and Processing,Nanostructure Research Center,Wuhan University of Technology,Wuhan,the People's Republic of China [5]Optics Valley Laboratory,Hubei,the People's Republic of China

出　　处：《InfoMat》2024年第10期53-64,共12页信息材料（英文）

基　　金：National Key Research and Development Program of China,Grant/Award Number:2023YFB4502200;National Natural Science Foundation of China,Grant/Award Numbers:52372149,U21A2069;Innovation Project of Optics Valley Laboratory,Grant/Award Number:OVL2023PY007;Guangdong HUST Industrial Technology Research Institute,Guangdong Provincial Key Laboratory of Manufacturing Equipment Digitization,Grant/Award Number:2023B1212060012;Interdiciplinary Research Program of HUST,Grant/Award Number:2024JCYJ008。

摘　　要：Local phase transition in transition metal dichalcogenides (TMDCs) by lithiumintercalation enables the fabrication of high-quality contact interfaces in twodimensional(2D) electronic devices. However, controlling the intercalation oflithium is hitherto challenging in vertically stacked van der Waalsheterostructures (vdWHs) due to the random diffusion of lithium ions in thehetero-interface, which hinders their application for contact engineering of 2DvdWHs devices. Herein, a strategy to restrict the lithium intercalation pathwayin vdWHs is developed by using surface-permeation assisted intercalationwhile sealing all edges, based on which a high-performance edge-contact MoS_(2)vdWHs floating-gate transistor is demonstrated. Our method avoids intercalationfrom edges that are prone to be random but intentionally promotes lithiumintercalation from the top surface. The derived MoS_(2) floating-gatetransistor exhibits improved interface quality and significantly reduced subthresholdswing (SS) from >600 to 100 mV dec^(–1). In addition, ultrafast program/erase performance together with well-distinguished 32 memory statesare demonstrated, making it a promising candidate for low-power artificialsynapses. The study on controlling the lithium intercalation pathways in 2DvdWHs offers a viable route toward high-performance 2D electronics for memoryand neuromorphic computing purposes.

关 键 词：2D vdW heterostructure high-speed floating-gate transistor interlayer lithium intercalation engineering phase-engineered contact 

分 类 号：TN32[电子电信—物理电子学]