High performance rapid single-flux-quantum bit-slice arithmetic logic unit  

作　　者：Jing Ren Pei-Yao Qu Jia-Hong Yang Xiang-Yu Zheng Hui Zhang Jie Ren Guang-Ming Tang 

机构地区：[1]State Key Lab of Processors,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China [2]University of Chinese Academy of Sciences,Beijing 100049,China [3]Shanghai Institute of Microsystem and Information Technology,Chinese Academy of Sciences,Shanghai 200233,China

出　　处：《Superconductivity》2024年第3期73-79,共7页超导（英文）

基　　金：Strategic Priority Research Program of Chinese Academy of Sciences,under Grant XDA18000000.

摘　　要：Two optimization technologies, namely, bypass and carry-control optimization, were demonstrated for enhancing the performance of a bit-slice Arithmetic Logic Unit (ALU) in 2n-bit Rapid Single-Flux-Quantum (RSFQ) microprocessors. These technologies can not only shorten the calculation time but also solve data hazards. Among them, the proposed bypass technology is applicable to any 2n-bit ALU, whether it is bit-serial, bit-slice or bit-parallel. The high performance bit-slice ALU was implemented using the 6 kA/cm^(2) Nb/AlOx/Nb junction fabrication process from Superconducting Electronics Facility of Shanghai Institute of Microsystem and Information Technology. It consists of 1693 Josephson junctions with an area of 2.46 0.81 mm^(2). All ALU operations of the MIPS32 instruction set are implemented, including two extended instructions, i.e., addition with carry (ADDC) and subtraction with borrow (SUBB). All the ALU operations were successfully obtained in SFQ testing based on OCTOPUX and the measured DC bias current margin can reach 86% - 104%. The ALU achieves a 100 utilization rate, regardless of carry/borrow read-after-write correlations between instructions.

关 键 词：High performance Rapid Single-Flux-Quantum(RSFQ) Arithmetic Logic Unit(ALU) Optimization technologies Superconducting integrated circuits 

分 类 号：O413[理学—理论物理]