大容量SRAM的时序设计  

Design of High-capacity SRAM Sequential

作　　者：李斌 曾健平[1] 陈君 徐磊 Li Bin

机构地区：[1]湖南大学物理与微电子科学学院,湖南长沙410082 [2]湖南省高正科技有限公司,湖南长沙410000

出　　处：《工业控制计算机》2024年第11期11-13,共3页Industrial Control Computer

摘　　要：随着集成电路技术的迅速发展,SRAM的容量越来越大,其时序也愈发难以控制。对SRAM的六管BitCell结构进行了分析,详细介绍了SRAM的工作原理和设计思路,并且给出了设计的SRAM版图布局,重点分析和解决了大容量SRAM面临的时序挑战。With the rapid development of integrated circuit technology,the capacity of SRAM is getting larger and larger,and its sequential is becoming more and more difficult to control.In this paper,the six-tube BitCell structure of SRAM is analyzed,the working principle and design ideas of SRAM are introduced in detail,and the layout of the SRAM of this design is given,focusing on the analysis and solution of the sequential challenges faced by large-capacity SRAM.

关 键 词：SRAM 时序电路 大容量 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TN40[自动化与计算机技术—计算机科学与技术]