基于缓冲器的ASIC芯片时序优化设计  

Timing optimization design of ASIC chip based on buffer

作　　者：张祥 赵启林 ZHANG Xiang;ZHAO Qilin(School of Electronics and Information Engineering,Shanghai University of Electric Power,Shanghai 201306,China;Moore Integrated Circuit Industry Development Co.,Ltd.,Shanghai 201306,China)

机构地区：[1]上海电力大学电子与信息工程学院,上海201306 [2]摩尔精英集成电路发展产业有限公司,上海201306

出　　处：《集成电路与嵌入式系统》2024年第12期33-37,共5页Integrated Circuits and Embedded Systems

摘　　要：超大规模集成电路制造工艺的飞速发展以及集成度的持续提高使得芯片时序收敛的难题日益凸显,时序作为数字芯片物理设计中的核心指标之一,其重要性不言而喻。在集成电路设计中,缓冲器的添加旨在优化扇出和降低互连线延迟,进而改善时序性能。然而,由于EDA工具在预测标准单元位置方面的局限性,自动插入缓冲器的方法可能存在不合理性。本文针对一款ASIC芯片的布局布线设计进行了深入探讨,采用Innovus作为设计工具,在布局阶段通过一种针对缓冲器插入的方法进行优化,实验结果表明,这一方法显著改善了布局布线后的设计结果,加速了时序的收敛过程。With the rapid development of very large-scale integration IC manufacturing process and the continuous improvement of integration,the difficulty of chip timing convergence has become increasingly prominent.The significance of timing,as one of the core indexes in the physical design of digital chips,cannot be underestimated.In integrated circuit design,buffers are added to optimize fan-out and reduce interconnect latency,thereby improving timing performance.However,due to the limitations of EDA tools in predicting the position of standard cells,the method of automatically inserting buffers may be unreasonable.This study conducted an in-depth exploration of the placement and route design of an ASIC chip using Innovus as a design tool.During the placement stage,an optimized method targeted at buffer insertion was employed.The experimental results indicate that this method significantly improved the design result after placement and route,accelerating the time sequence convergence process.

关 键 词：时序 缓冲器 ASIC芯片 时钟树综合与布局 

分 类 号：TN402[电子电信—微电子学与固体电子学]