基于真单向时钟正沿触发寄存器的边沿触发器设计  

Design of Edge Trigger based on True Unidirectional Clock Positive Edge Trigger Register

作　　者：朱宏宇 聂海[1] ZHU Hongyu;NIE Hai(College of Communacation Engineering,Chengdu University of Information Technology,Chengdu 610225,China)

机构地区：[1]成都信息工程大学通信工程学院,四川成都610225

出　　处：《成都信息工程大学学报》2024年第6期654-659,共6页Journal of Chengdu University of Information Technology

基　　金：四川省科技计划资助项目(2022YFG0003)。

摘　　要：针对锁相环电路中鉴频鉴相器(PFD)和分频器传输速度的问题,设计搭建了一种基于真单向时钟正沿触发寄存器(TSPC)的边沿触发器。实现了在1 GHz频段高速传输的功能,且结构简单、传输延迟短和功耗低等优点。传统的主从式D触发器(MS DFF)采用多个传输门和反相器级联的结构,传输延迟大且有较大的传输功耗,锁相环电路也因此受到极大的限制;而基于TSPC的D触发器采用动态逻辑架构,将传输的数字信息储存于动态刷新逻辑中,以极简单的结构和较少的晶体管实现了信息储存和传输的功能。在仿真软件中对两种结构的DFF分别进行仿真,仿真得出所设计的TSPC DFF在500 MHz频率下传输延时为70 ps,而传统MS DFF在同样环境传输延时为120 ps,TSPC DFF较于MS DFF在高频传输下有着明显的优势。Aiming at the problem of the transmission speed of frequency Phase detector(PFD)and frequency divider in a PLL circuit,an edge trigger based on a true unidirectional clock positive edge trigger register(TSPC)was designed and built.This structure achieves high-speed transmission in the 1 GHz frequency band and has the advantages of simple structure,short transmission delay,and low power consumption.The traditional master-slave D flip-flop(MS DFF)adopts a cascaded structure of multiple transmission gates and inverters,resulting in high transmission delay and high transmis-sion power consumption,which greatly limits the phase-locked loop circuit;The D trigger based on TSPC adopts a dynam-ic logic architecture,storing the transmitted digital information in the dynamic refresh logic,and achieves the function of information storage and transmission with an extremely simple structure and fewer transistors.Two types of DFFs with dif-ferent structures were simulated in the simulation software.The simulation results showed that the designed TSPC DFF has a transmission delay of 70 ps at 500 MHz,while the traditional MS DFF has a transmission delay of 120 ps in the same environment.TSPC DFF has significant advantages over MS DFF in high-frequency transmission.

关 键 词：TSPC MS DFF 动态刷新逻辑 高频 低传输延迟 

分 类 号：TN432[电子电信—微电子学与固体电子学]