基于FPGA的时基设计和时基非线性补偿  

FPGA-based Time base Design and Time base Nonlinear Compensation

作　　者：李佳 邓庚会 陈永强[1] LI Jia;DENG Genghui;CHEN Yongqiang(College of Communication Engineering(microelectronic),Chengdu University of Information Technology,Chengdu 610225,China;School of Aeronautics and Astronautics,University of Electronic Science and Technology of China,Chengdu 611731,China)

机构地区：[1]成都信息工程大学通信工程(微电子)学院,四川成都610225 [2]电子科技大学航空航天学院,四川成都611731

出　　处：《成都信息工程大学学报》2024年第6期660-664,共5页Journal of Chengdu University of Information Technology

摘　　要：为提高宽带时域反射计的等效采样率和时基分辨率,设计一种基于现场可编程门阵列(field programma-ble gate array,FPGA)的时域反射计数据采集模块的时基方案,并设计一种基于查找表的时基校准方法对时基非线性进行补偿。该方法基于等精度测频法,使用FPGA测量该方波信号的频率,得到准确的延迟时间以实现查找表的建立。并利用采样芯片的微调引脚实现1 ps步进的顺序等效采样和时基非线性实时补偿。实测数据表明:设计的时基采样方案实现了1 TSa/s等效采样率,时基补偿方案使时基非线性减小至-0.8~1 ps。To improve the equivalent sampling rate and resolution of a high-bandwidth time domain reflectometer(TDR),this paper designs a field-programmable gate array(FPGA)-based time base scheme for time domain reflecto-meter data acquisition module,and a lookup table-based time base calibration method designed to compensate for the time base nonlinearity.The method is based on the equal precision frequency measurement method,which uses the FP-GA to measure the frequency of this square wave signal to get the accurate delay time for the lookup table and the trim pin of the sampling chip to achieve the sequential equivalent sampling in 1 ps steps and the time-base nonlinearity com-pensation in real-time.The measured data show that the designed time base sampling scheme achieves a 1 TSa/s equiva-lent sampling rate and the time base compensation scheme reduces the time base nonlinearity to the range of-0.8-1 ps.

关 键 词：顺序等效采样 现场可编程门阵列 数据采集模块 数模转换器 采样时基 

分 类 号：TN929.52[电子电信—通信与信息系统]