基于UIS测试的Si/SiC级联器件雪崩特性分析  

Avalanche Performance Analysis of Si/SiC Cascode Device Based on UIS Test

作　　者：周郁明[1] 王倩[1] 张秋生 刘航志 ZHOU Yuming;WANG Qian;ZHANG Qiusheng;LIU Hangzhi(Anhui University Key Laboratory of Power Electronics and Motion Control,Anhui University of Technology,Anhui Ma’anshan 243002,China)

机构地区：[1]安徽工业大学安徽省高校电力电子与运动控制重点实验室,安徽马鞍山243002

出　　处：《高压电器》2024年第12期113-121,131,共10页High Voltage Apparatus

基　　金：安徽省自然科学基金资助项目(2008085ME157)。

摘　　要：与机械式断路器相比,使用半导体功率器件构成的直流固态断路器在响应时间方面有较大的优势。由低压硅金属—氧化物—半导体场效应晶体管(Si MOSFET)和高压碳化硅结型场效应晶体管(SiC JFET)构成的Si/SiC级联型器件具有优异的开断特性。半导体功率器件可靠性一直是直流固态断路器所关注的焦点问题,非箝位感性负载开关(unclamped inductive switching,UIS)测试是评估半导体功率器件可靠性的重要方法。文中通过实验和仿真的方式分析了Si/SiC级联器件在非箝位感性负载开关过程的雪崩特性。首先,通过增加器件导通时间得到了不同负载电流下的雪崩特性,结果表明,随着导通时间的增加,Si/SiC级联器件在雪崩期间出现了雪崩电压下降的异常特性。随后,通过分立式Si/SiC级联器件进行UIS测试,发现异常特性是由于SiC JFET在雪崩期间出现导通而形成的。最后,通过Si/SiC级联器件的三维电—热耦合仿真,结果表明雪崩期间SiC JFET芯片栅极铝金属层和键合线温度升高,导致SiC JFET栅极等效电阻增加,最终使得SiC JFET在雪崩期间出现导通。Compared to mechanical circuit breaker,DC solid⁃state circuit breaker(SSCB)composed of semiconduc⁃tor devices has great advantage in response time.The Si/SiC cascode element consisting of low⁃voltage silicon metal⁃oxide⁃semiconductor field⁃effect transistor(Si MOSFET)and high⁃voltage silicon carbon junction field⁃effect transis⁃tor(SiC JFET)has excellent switching characteristics.The reliability of semiconductor power element has always been the focus of DC SSCB.The test of the unclamped inductive switching(UIS)is an important method to assess reli⁃ability of the semiconductor power element.In this paper,the avalanche performance of Si/SiC cascode element dur⁃ing the UIS period is analyzed by means of experiment and simulation.Firstly,the avalanche performance under dif⁃ferent load currents is obtained by increasing the on⁃time of the element.The results show that with the increase of the on⁃time the Si/SiC cascade element shows an abnormal performance of the avalanche⁃voltage drop during the ava⁃lanche period.Then,UIS tests is performed through a discrete Si/SiC cascode element,finding that the abnormal per⁃formance originates from the turn⁃on of SiC JFET during avalanche period.Finally,the 3D electrical⁃thermal cou⁃pling simulation of the Si/Sic cascade element is performed.The results show that the temperature of aluminum metal layer and bonding wire of SiC JFET rises during the avalanche period,leading to the increase of the gate equivalent⁃resistance of SiC JFET,and ultimately resulting in the turn⁃on of SiC JFET during the avalanche period.

关 键 词：固态断路器 Si/SiC级联器件 雪崩特性 电—热耦合仿真 

分 类 号：TM561[电气工程—电器] TN386[电子电信—物理电子学]