Dynamic Write-Voltage Design and Read-Voltage Optimization for MLC NAND Flash Memory  

作　　者：Cai Runbin Fang Yi Shi Zhifang Dai Lin Han Guojun 

机构地区：[1]School of Information Engineering,Guangdong University of Technology,Guangdong 510006,China

出　　处：《China Communications》2024年第12期297-308,共12页中国通信（英文版）

基　　金：supported in part by the NSF of China under Grants 62322106,62071131,U2001203,61871136;the Guangdong Basic and Applied Basic Research Foundation under Grant 2022B1515020086;the International Collaborative Research Program of Guangdong Science and Technology Department under Grant 2022A0505050070;the Industrial R&D Project of Haoyang Electronic Co.,Ltd.under Grant 2022440002001494.

摘　　要：To mitigate the impact of noise and inter-ference on multi-level-cell(MLC)flash memory with the use of low-density parity-check(LDPC)codes,we propose a dynamic write-voltage design scheme con-sidering the asymmetric property of raw bit error rate(RBER),which can obtain the optimal write voltage by minimizing a cost function.In order to further improve the decoding performance of flash memory,we put forward a low-complexity entropy-based read-voltage optimization scheme,which derives the read voltages by searching for the optimal entropy value via a log-likelihood ratio(LLR)-aware cost function.Simulation results demonstrate the superiority of our proposed dynamic write-voltage design scheme and read-voltage optimization scheme with respect to the existing counterparts.

关 键 词：error correction coding multi-level-cell(MLC) NAND flash memory read voltage write voltage 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TN911.22[自动化与计算机技术—计算机科学与技术]