带逻辑校正的低延时低功耗高电平移位电路  

Low Delay and Low Power Consumption High-level Shift Circuit with Logic Correction

作　　者：蒋志林 姜岩峰 于平平 JIANG Zhilin;JIANG Yanfeng;YU Pingping(Engineering Research Center of IoT Technology Applications(Ministry of Education),Department of Electronic Engineering,Jiangnan University,Wuxi 214122,China)

机构地区：[1]江南大学电子工程系物联网技术应用教育部工程研究中心,无锡214122

出　　处：《电源学报》2024年第6期304-310,共7页Journal of Power Supply

基　　金：国家自然科学基金资助项目(61774078,51802124);江苏省自然科学基金资助项目(BK20180626)。

摘　　要：提出1种带有逻辑校正功能的新型低延时低功耗的低电平到高电平的移位电路。该电路采用低延时电平移位电路与低功耗电平移位电路并行工作,在逻辑校正无误后将1.0~1.5 V的低电平转换为5 V的高电平,可广泛应用于GaN驱动电路中。基于0.5μm的BCD工艺,将1.5V的电源低压和5 V的电源高压在5 MHz频率下对该电路进行验证。结果表明,该电路虽版图面积有所增加,但上升和下降延时分别降低至2.3ns和1.8ns,总功耗电流仅为11μA。A novel low delay and low power consumption low-to-high level shift circuit with a logic correction function is proposed,which uses a low delay level shift circuit and a low power consumption level shift circuit to work in parallel.After the logic is corrected,the low level between 1 V and 1.5 V is converted to a high level of 5 V,so this circuit can be widely applied in GaN driver circuits.Based on the 0.5μm BCD process,1.5 V power supply low voltage and 5 V power supply high voltage,the circuit is verified at 5 MHz.Results show that although the layout area of this circuit increases as a whole,the rise and fall delays are reduced to 2.3 ns and 1.8 ns,respectively,with a total power consumption current of only 11μA.

关 键 词：高电平移位 逻辑校正 低功耗 低延时 GaN驱动 

分 类 号：TN386[电子电信—物理电子学]