Joint device architecture algorithm codesign of the photonic neural processing unit  

作　　者：Li Pei Zeya Xi Bing Bai Jianshuai Wang Jingjing Zheng Jing Li Tigang Ning 

机构地区：[1]Beijing Jiaotong University,Institute of Lightwave Technology,Key Lab of All Optical Network&Advanced Telecommunication Network of EMC,Beijing,China [2]Photoncounts(Beijing)Technology Co.Ltd.,Beijing,China

出　　处：《Advanced Photonics Nexus》2023年第3期132-138,共7页先进光子学通讯（英文）

基　　金：supported by the National Natural Science Foundation of China(Grant No.61827817)。

摘　　要：The photonic neural processing unit(PNPU)demonstrates ultrahigh inference speed with low energy consumption,and it has become a promising hardware artificial intelligence(AI)accelerator.However,the nonidealities of the photonic device and the peripheral circuit make the practical application much more complex.Rather than optimizing the photonic device,the architecture,and the algorithm individually,a joint device-architecture-algorithm codesign method is proposed to improve the accuracy,efficiency and robustness of the PNPU.First,a full-flow simulator for the PNPU is developed from the back end simulator to the high-level training framework;Second,the full system architecture and the complete photonic chip design enable the simulator to closely model the real system;Third,the nonidealities of the photonic chip are evaluated for the PNPU design.The average test accuracy exceeds 98%,and the computing power exceeds 100TOPS.

关 键 词：OPTICS PHOTONICS Mach-Zehnder interferometer array photonic neural processing unit design 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]