高精度两步分支混合CORDIC算法设计及FPGA实现  

Design and FPGA implementation of a high-precision double step branching hybrid CORDIC algorithm

作　　者：陈小文[1,2] 芮志超 朱麒瑾 董羽 孟宇 CHEN Xiao-wen;RUI Zhi-chao;ZHU Qi-jin;DONG Yu;MENG Yu(College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;Key Laboratory of Advanced Microprocessor Chips and Systems,Changsha 410073,China)

机构地区：[1]国防科技大学计算机学院,湖南长沙410073 [2]先进微处理器芯片与系统重点实验室,湖南长沙410073

出　　处：《计算机工程与科学》2024年第12期2099-2108,共10页Computer Engineering & Science

摘　　要：CORDIC(坐标旋转数字计算机)算法是一种用于计算三角函数和其他数学运算的算法,被广泛应用于数字信号处理、计算机图形学等领域。CORDIC算法仅需要加减和移位运算,特别适合布署在硬件平台。传统CORDIC算法的局限在于迭代次数过多,虽然不少研究对此进行了优化,但也增加了硬件开销且易造成精度丢失。为此,基于Hybrid CORDIC算法和Double step branching CORDIC算法,给出了一种CORDIC优化算法——高精度两步分支混合CORDIC(HD CORDIC)算法。该算法在迭代次数上减少到N/4+“1”(N为微旋转角度个数及位宽),并给出了新的混合角度集的划分公式,以达到ε<2-(N-2)的高精度,与基本CORDIC算法(ε<2-(N-1))相近,且不用计算缩放因子K。HD CORDIC算法采用流水线结构,流水线级数仅为N/4+3(不含缩放因子补偿操作的基本CORDIC算法为N+2)。采用Verilog对所提算法进行了硬件实现,并在XILINX Zynq-7000 xc7z100ffv900-2 FPGA平台上进行了综合,实验评估显示,当输入角度位宽为16时,工作频率为315.66 MHz,完成1次正余弦函数运算仅需6个时钟周期。相比于XILINX CORDIC IP,HD CORDIC算法处理时间减少了59.13%,LUT开销减少了55.74%,Register开销减少了80.24%,功耗降低了35.99%。The CORDIC(coordinate rotation digital computer)algorithm is an approach used for computing trigonometric functions and other mathematical operations.It is widely applied in complex fields such as digital signal processing and computer graphics.The CORDIC algorithm,which only requires addition,subtraction,and shift operations,is particularly suited for hardware implementation.A limitation of the traditional CORDIC algorithm is its excessive number of iterations.Many studies have aimed to optimize this,but these optimizations often increase hardware overhead and may lead to precision loss.To address this,this paper proposes an optimized CORDIC algorithm based on the Hybrid CORDIC algorithm and the double step branching CORDIC algorithm,called high-precision double step branching hybrid CORDIC(HD CORDIC)algorithm.This algorithm reduces the number of iterations to N/4+“1”(where N is the number of micro-rotation angles and the bit width),presents a new parti-tioning formula for the hybrid radix set to achieve high precision ofε<2-(N-2),which is similar to the basic CORDIC algorithm(ε<2-(N-1)),and does not require the calculation of the scaling factor K.The HD CORDIC algorithm employs a pipelined architecture with only N/4+3 pipeline stages(while the basic CORDIC algorithm without scaling factor compensation operation is N+2).This algorithm was implemented in hardware using Verilog and synthesized on the XILINX Zynq-7000 xc7z100ffv900-2 FPGA platform.Experimental results show that when the input angle bit width is 16,the operating frequency is 315.66 MHz and it only takes 6 clock cycles to complete one sine&cosine function operation.Compared with the XILINX CORDIC IP,the HD CORDIC algorithm reduces the processing time by 59.13%,the LUT overhead by 55.74%,the register overhead by 80.24%,and the power consumption by 35.99%.

关 键 词：CORDIC优化算法 Hybrid CORDIC架构 两步分支 三角函数 现场可编程门阵列 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]