一种面向SDH应用的低抖动全数字锁相环  

Low Jitter All-digital Phase-locked Loop for SDH Application

作　　者：赵雅欣 秦浩翔 刘川萍 何进[1] ZHAO Yaxin;QIN Haoxiang;LIU Chuanping;HE Jin(School of Physics and Technology,Wuhan University,Wuhan 430072,P.R.China)

机构地区：[1]武汉大学物理科学与技术学院,武汉430072

出　　处：《微电子学》2024年第4期570-576,共7页Microelectronics

摘　　要：为使同步数字体系(Synchronous Digital Hierarchy,SDH)设备获得高质量的时钟信号源,提出了一种使用8 kHz输入时钟信号综合出低抖动9.72 MHz输出时钟信号的全数字锁相环(All-Digital Phase-Locked Loop,ADPLL)。该ADPLL使用了一种新型的滤波式鉴相器,通过特定的算法实现了对极低占空比周期信号的相位检测和比较,并结合数控振荡器对输出时钟信号进行调整,使得9.72 MHz输出时钟信号具备低抖动特性。该设计在Xilinx的Pynq-Z2上进行了验证,测试结果表明,ADPLL锁定范围为7.99836 kHz~8.00164 kHz,相应的输出时钟信号范围为9.7180074 MHz~9.7219926 MHz,9.72 MHz输出时钟信号峰峰值抖动仅为1.6 ns@9.72 MHz,约为0.016UI,远低于ITU-T G.813规范的要求(0.5UI)。To obtain a high-quality clock source for Synchronous Digital Hierarchy(SDH)devices,this study proposes an all-digital phase-locked loop(ADPLL)that synthesizes a low-jitter 9.72 MHz output clock signal using an 8-kHz input reference clock signal.The ADPLL employs a new design of a filtered phase detector,which realizes the detection and comparison of extremely low-duty cycle signals using a specific algorithm,and adjusts the output clock signal using a digitally controlled oscillator to obtain the 9.72-MHz output clock signal with low jitter.The design is implemented on the Xilinx Pynq-Z2 board.The test result shows that the lock range of the ADPLL is 7.998368.00164 kHz,and the corresponding output clock signal range is 9.71800749.7219926 MHz.The peak-to-peak jitter of the 9.72-MHz output clock signal is only 1.6 ns,approximately 0.016 UI,which is significantly lower than the requirement of ITU-T G.813 recommendation(0.5UI).

关 键 词：全数字锁相环(ADPLL) 滤波式鉴相器 低抖动 FPGA SDH设备时钟 

分 类 号：TN911.8[电子电信—通信与信息系统]