一种高速高精度电流舵DAC的设计  

Design of a High-speed and High-resolution Current Steering DAC

作　　者：唐雨潇 蒋颖丹[2] 万发雨[1] 苏小波[2] 吴江 盛炜[2] TANG Yuxiao;JIANG Yingdan;WAN Fayu;SU Xiaobo;WU Jiang;SHENG Wei(School of Electronic and Information Engineering,Nanjing University of Information Science and Technology,Nanjing,Jiangsu 210044,P.R.China;The 58th Research Institute of China Electronics Technology Group,Wuxi,Jiangsu 214000,P.R.China)

机构地区：[1]南京信息工程大学电子与信息工程学院,南京210044 [2]中国电子科技集团第五十八研究所,江苏无锡214000

出　　处：《微电子学》2024年第4期577-583,共7页Microelectronics

基　　金：国家重点研发计划(2022YFE0122700)。

摘　　要：针对电流舵DAC高频下因时钟馈通而导致动态性能指标降低的缺点,提出了一种自适应开关限幅单元,通过对摆幅进行限制从而减少了馈通效应,并且结合开关驱动电路改变了栅极控制信号交叉点的位置,降低开关翻转引入的毛刺,提高了无杂散动态范围。采用了CMOS 0.18μm工艺,结合四项开关等其他结构,设计了一种16位1.5 GSPS的电流舵DAC,并对DAC的性能进行了仿真和测试。测试结果表明DAC拥有良好的线性度,在1.5 GSPS采样率和70 MHz输入频率的情况下,无杂散动态范围(SFDR)为78.59 dB,动态性能良好。This study introduces an adaptive switching limiter unit to address the limitations of the low dynamic performance of the current-rudder DAC due to clock feed-through at high frequencies.By limiting the amplitude of the swing,the feed-through effect is reduced.Combined with a switch drive circuit,the position of the grid control signal crossing point is changed.As a result,the burrs introduced by switch flipping were reduced,and the spurious free dynamic range was improved.A 16-bit 1.5 GSPS current-steering DAC is designed using CMOS 0.18μm technology combined with a quad-phase switch and other structures,and the performance of the DAC was simulated and tested.The test results showed that the DAC exhibited good linearity,the spurious free dynamic range was 78.59 dB at 1.5 GSPS sampling rate and 70 MHz input frequency,and the dynamic performance was good.

关 键 词：数模转换器 开关限幅 四相开关 无杂散动态范围 

分 类 号：TN432[电子电信—微电子学与固体电子学]