基于悬浮电源动态放大器的Delta-Sigma调制器  

Design a Delta-Sigma Modulator Using a Cascoded Floating-inverter-based Dynamic Amplifier

作　　者：李海鸥[1] 王媛 翟江辉[1] 奥鹏龙 秦关明 LI Hai’ou;WANG Yuan;ZHAI Jianghui;AO Penglong;QIN Guanming(Guilin Univ.of Elec.Technol,Guangxi Key Lab.of Precision Naviga.Technol.and Applic,Guilin,Guangxi 541004,P.R.China)

机构地区：[1]桂林电子科技大学广西精密导航技术与应用重点实验室,广西桂林541004

出　　处：《微电子学》2024年第4期584-589,共6页Microelectronics

基　　金：国家自然科学基金面上项目(62174041);广西自然科学基金创新研究团队项目(2018GXNSFGA281004);云南省科技重大专项计划新材料专项(202102AB080008-2);广西研究生教育创新计划项目(YCSW2023305,YCSW2022273)。

摘　　要：采用SMIC 180 nm CMOS工艺,设计了一款低功耗3阶3 bit Delta-Sigma调制器(DSM)。该调制器工作于半周期相位,积分器采用共源共栅型悬浮电源动态放大器(FIA)结构,该结构能够有效降低电路功耗,通过使用多位量化器提高信噪比,并采用数据加权平均(DWA)技术抑制调制回路中因匹配单元误差引起的非线性失真。调制器工作于2.5 MHz,信号带宽20 kHz,仿真得到,在1.2 V的电源电压下功耗为113μW,SNR/SNDR为98.77/98 dB。We employed the SMIC 180-nm CMOS process to design a low-power,3rd order,3-bit delta-sigma modulator(DSM).The modulator operated in a half-delay phase.The integrator utilized a cascaded floating-inverter-based dynamic amplifier(FIA)structure,which effectively reduces the power consumption of the circuit.The signal-to-noise ratio was enhanced by using a multi-bit quantizer,and non-linear distortion caused by a unit mismatch in the feedback loop was suppressed using data-weighted averaging(DWA)technology.The modulator operated at 2.5 MHz with a signal bandwidth of 20 kHz.The simulation results showed that the power consumption was 113μW under a power supply voltage of 1.2 V,and the SNR/SNDR was 98.77/98 dB.

关 键 词：模数转换器 DELTA-SIGMA调制器 动态放大器 悬浮电源动态反相放大器 

分 类 号：TN792[电子电信—电路与系统]