基于FPGA的Midori算法优化实现  

Optimized Implementation of the Midori Algorithm Based on FPGA

作　　者：董秀则[1] 杨鸿刚 马绪健 DONG Xiuze;YANG Honggang;MA Xujian(Beijing Electronic Science and Technology Institute,Beijing 100070,P.R.China)

机构地区：[1]北京电子科技学院,北京市100070

出　　处：《北京电子科技学院学报》2024年第4期1-8,共8页Journal of Beijing Electronic Science And Technology Institute

基　　金：中央高校基本科研业务费资金资助项目(3282023005,328202252)。

摘　　要：Midori是一种高效的轻量级分组密码算法,具有安全灵活、易于实现等特点,可应用于资源受限环境。通过分析算法的加密流程,本文引入了一种在FPGA上的实现方案,通过在单个时钟周期内完成Midori-64算法两轮加密迭代,将算法的16轮迭代运算优化至8轮,有效减少了所需的时钟周期数量,从而提高性能。通过在Xilinx ISE Design Suite 147上综合后,最终实现的吞吐率达16307Mbps,频率为22931MHz,与现有研究相比本方案吞吐率分别提高25%和51%。Midori is an efficient and lightweight block cipher algorithm known for its security,flexibil⁃ity,and ease of implementation,making it suitable for resource⁃constrained environments.By analyzing the encryption process of the algorithm,this paper introduces an FPGA implementation scheme.By completing two rounds of Midori-64 encryption iterations in a single clock cycle,the 16-round iterative computation of the algorithm is optimized to 8 rounds,effectively reducing the required number of clock cycles and thereby improving performance.After synthesis in the Xilinx ISE Design Suite 14.7,the fi⁃nal implementation achieves a throughput of 1630.7 Mbps and a frequency of 229.31 MHz.Compared to existing studies,this scheme improves the throughput by 25%and 51%,respectively.

关 键 词：Midori 双轮迭代 轻量级分组密码 FPGA 

分 类 号：TN918[电子电信—通信与信息系统]