基于UVM的时间敏感网络交换芯片的验证架构设计  

UVM-based verification architecture design for TSN time-sensitive network switch chip

作　　者：赵伟 陈三伟 方震 何泉初 王雨亭 Zhao Wei;Chen Sanwei;Fang Zhen;He Quanchu;Wang Yuting(No.58 Research Institute of China Electronics Technology Group Corporation,Wuxi 214035,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子技术应用》2024年第12期36-40,共5页Application of Electronic Technique

摘　　要：基于UVM验证方法学、自动化比对和覆盖率驱动的验证思想,构建了一个用于时间敏感网络(TSN)交换芯片的系统验证架构。该架构采用分类和流水处理数据报文方法,结合流量检测、时间槽检测和数据报文自动化比对方案,成功支撑TSN业务系统验证方法落地,保证了系统验证完备性。芯片回片经测试满足商用需求,再次论证了验证架构的完备性。In this paper,a system verification architecture for time-sensitive network(TSN)switch chip,which is based on UvM,automatic comparison and coverage-driven verification thinking,is designed.This architecture adopts the method of classi-fying and pipelining packets,combined with traffic detection,time slot detection and packets automatic comparison scheme,suc-cessfully satisfies the implementation of the TSN system verification method,finally ensures the system verification completion.Chip test results meet commercial requirements,once again demonstrates verification architecture completeness.

关 键 词：UVM 时间敏感网络 TSN 交换芯片 系统验证 

分 类 号：TN402[电子电信—微电子学与固体电子学]