CPLD实现快速低开关损耗的优化SVPWM算法  

Complex Programmale Logic Device Applied to Optimized SVPWM Algorithm

作　　者：李明峰[1] 林平[1] 张仲超[1] 

机构地区：[1]浙江大学,杭州310027

出　　处：《电力电子技术》2002年第6期61-63,共3页Power Electronics

摘　　要：介绍了利用ALTERA公司的MaxplusⅡ软件及ACEX芯片 ,基于一种用于三相电压型逆变器的优化SVPWM算法 ,来实现变频调速系统 ,该算法采纳Kohonen神经网络的优点。选择适当的调制方法和改进的算法不但可以显著地缩短计算时间 ,且显著减少开关损耗。用复杂可编程逻辑器件 (CPLD)来实现这种算法非常简单合适。This paper introduces the new CPLD devices, e.g.ALTERA'sAbstract: This paper introduces the new CPLD devices, e.g.ALTERA'sACEX chip and EDA tool Maxplus Ⅱ.Using them a new algorithm of space vector PWM for three-phase voltage inverter is complemented, which takes the advantages of Kohonen neural network.Waveform shows the switching losses can be extremely reduced,and calculating time is obviously shortened by choosing proper modulation method and algorithm.This algorithm is easily realized by using CPLD.

关 键 词：CPLD 低开关损耗 优化 SVPWM算法 交流电机 变频调速 脉宽调制 空间矢量 神经网络 复杂可编程逻辑器件 

分 类 号：TM34[电气工程—电机]