编译指导的多线程低功耗技术研究  

A STUDY OF THE COMPILER-DIRECTED LOW POWER MULTITHREADING TECHNOLOGY

作　　者：赵荣彩[1] 唐志敏[1] 张兆庆[1] Guang R.Gao 

机构地区：[1]中国科学院计算技术研究所系统结构室,北京100080 [2]美国特拉华大学电子与计算机工程系,特拉华州纽瓦克19711

出　　处：《计算机研究与发展》2002年第12期1572-1579,共8页Journal of Computer Research and Development

基　　金：国家"八六三"高技术研究发展计划基金资助 (2 0 0 1AA1110 70 )

摘　　要：多线程和低功耗将是研究下一代微处理器结构所要解决和实现的重点目标之一 .提出了一个在 SMT体系结构中通过动态调整 CPU执行频率降低功耗的计算模型 ,进一步分析和讨论了如何在编译时识别具有可使处理部件降低频率执行的期望区间 ,并给出了调整频率和能量分析的计算模型以及编译实现策略 ,目的是在不降低或不明显降低程序执行性能的情况下 ,显著降低处理器的功率 /能量消耗 .理论上该模型也可以用于Multithreading and low power is one of the main goals to be studied, solved and realized for next generation micro architecture. A power model based on SMT (simultaneous multithreading) architecture for scaling the dynamic frequency of function units to decrease the CPU power/energy consumption is proposed in this paper. Further more, how to recognize the regions being possible for scaling the execution frequency at compile time is analyzed and discussed, the models for computing the scaling frequency and analyzing the energy consumption are given also, and then the compile policy is proposed. The goal is to save more significant power/energy without an apparent degradation in performance. In theory, this model can also be used to superscalar and multiprocessor architectures.

关 键 词：多线程 低功耗技术 微处理器 体系结构 编译优化 

分 类 号：TP332[自动化与计算机技术—计算机系统结构] TP314[自动化与计算机技术—计算机科学与技术]