多路并行延迟锁相式射频DAC设计  

A Multi-channel Input and DLL Based Structure for RF DACs

作　　者：蒋颖丹[1] 苏小波[1] 杨霄垒 赵霖[1] 

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《固体电子学研究与进展》2015年第5期472-477,共6页Research & Progress of SSE

摘　　要：提出了一种适用于2GS/s以上速率射频DAC设计的结构——多路并行延迟锁相式DAC,并基于该结构实现了一款14位2.5GS/s高性能DAC。测试结果显示:积分非线性误差INL为±0.5LSB,微分非线性误差DNL为±0.4LSB;2.5GS/s转换速率条件下,输出100 MHz正弦波时SFDR为67.08dBc,IMD达到93.08dBc,输出550 MHz正弦波时,SFDR为56.42dBc。A multi-channel input and DLL based structure for RF DACs with rates of 2GS/s and above was proposed.A 14 bit 2.5 GS/s DAC was designed based on this structure.The measured DNLand INLare ±0.4LSB and ±0.5LSB,respectively.The measured SFDRis67.08 dBc at 2.5GS/s clock rate and 100 MHz output frequency,56.42 dBc at 2.5GS/s clock rate and 550 MHz output frequency.The measured IMD centered at 100 MHz with 2.5GS/s conversion rate is up to 93.08 dBc.

关 键 词：多路并行 延迟锁相 射频数模转换器 电流舵 

分 类 号：TN792[电子电信—电路与系统]