CMOS低相位噪声频率合成器设计  

Design of CMOS Low Phase-noise Frequency Synthesizer

作　　者：陈艳[1] 黄灿英[1] 沈放[1] 涂剑鹏[1] 

机构地区：[1]南昌大学科学技术学院,南昌330029

出　　处：《固体电子学研究与进展》2015年第6期537-544,共8页Research & Progress of SSE

基　　金：江西省教育改革课题(JXJG-14-28-3;JXJG-14-28-1;JXJG-14-28-8);江西省教育改革课题(JXJG-13-28-6);江西省教育厅青年科学基金资助项目(GJJ12165);江西省教育教学"十二五"规划课题(11YB452)

摘　　要：基于工业自动化无线网络的需求,设计了一款低相位噪声小数分频频率合成器。频率合成器通过采用一个1.4~2.2GHz超低压控灵敏度压控振荡器和可调同相/正交分频器,能够实现在220~1 100 MHz范围内产生同相/正交信号。此外,还采用了相位开关预分频器用于降低锁相环相位噪声,自校准充电荷泵用于抑制过冲,相位频率检波器用于缩短稳定时间。频率合成器采用TSMC 0.18μm CMOS工艺制造,芯片面积1.2mm2,供电电压1.8V,功耗仅为15mW。在200kHz环路带宽内,测得的最小相位噪声在10kHz和1 MHz频偏时分别为-106dBc/Hz和-131dBc/Hz,能够在13.2μs内达到稳定。In this paper,a low phase-noise fraction-N frequency synthesizer was proposed for wireless networks of industrial automation(WIA)application.The proposed frequency synthesizer could provide in-phase/quadrature-phase(I/Q)signal in 220~1 100 MHz by adopting a 1.4~2.2GHz ultra-low gain voltage-controlled oscillator(VCO)and a tunable I/Q divider.In addition,aphase-switch prescaler was employed to reduce PLL phase noise,a self-calibrated charged pump was adopted to suppress spur and a phase frequency detector was used to reduce settling time.The frequency synthesizer was realized in TSMC 0.18μm CMOS technology.The chip size is 1.2mm2 and the power dissipation is 15 mW in 1.8Vsupply.Measured results show the frequency synthesizer has a phase noise of-106dBc/Hz and-131dBc/Hz at 10 kHz and 1MHz offset,respectively,and could settle within 13.2μs.

关 键 词：压控振荡器 同相/正交分频器 相位开关预分频器 电荷泵 低相位噪声 频率合成器 

分 类 号：TN74[电子电信—电路与系统]