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作 者:沈诗雅 杨俊浩[1] 张沁枫 魏敬和[1,2] SHEN Shiya;YANG Junhao;ZHANG Qinfeng;WEI Jinghe(The 58th Research Institute of China Electronics Technology Group Corporation,Wuxi,Jiangsu,214035,CHN;National Key Laboratory of Integrated Circuits and Microsystems,Wuxi,Jiangsu,214035,CHN)
机构地区:[1]中国电子科技集团公司第五十八研究所,江苏无锡214035 [2]集成电路与微系统全国重点实验室,江苏无锡214035
出 处:《固体电子学研究与进展》2024年第6期591-597,共7页Research & Progress of SSE
基 金:江苏省自然科学基金(BK20211041)。
摘 要:基于0.18μm SiGe BiCMOS工艺提出了一种低电流失配的鉴频鉴相器和电荷泵。鉴频鉴相器采用改进的边沿触发型结构,D触发器和与门等模块均基于电流模逻辑,能够抑制共模噪声并减小鉴相死区;电荷泵中设计了电流补偿偏置电路,能够减小沟道长度调制效应等因素的影响,降低电流失配。通过抑制鉴频鉴相器和电荷泵的上述非理想效应可以降低其造成的相位误差,进而优化锁相环的带内相噪。在典型工艺角下,3.3 V电源电压供电,电荷泵输出电流为3.2 mA时,补偿后0.7~2.8 V电压范围内充放电电流失配度小于1%,鉴频鉴相器和电荷泵电流噪声为-214.199 dBA/Hz@100 kHz。流片测试得到锁相环的相位噪声为-138.34 dBc/Hz@100 kHz,表明设计的鉴频鉴相器和电荷泵具有低电流失配和低带内相位噪声。A low current mismatch phase frequency detector(PFD) and charge pump(CP) was proposed based on the 0.18 μm SiGe BiCMOS process.The PFD employed an improved edge-triggered structure,modules such as D flip-flops and sum gate were based on current-mode logic,which served to suppress common-mode noise and minimize the dead zone.The CP was designed with a current-compensated bias circuit,which can reduce the impact of factors such as the channel-length modulation effect,then reduce current mismatch.By suppressing the aforementioned non-ideal effects of the PFD and CP,the phase error caused by them can be reduced,thus optimizing the in-band phase noise of the phase-locked loop(PLL).In the typical process corner,with a 3.3 V supply voltage and 3.2 mA output current of the CP,the charge/discharge current mismatch is less than 1% in the voltage range of 0.7-2.8 V after compensation.The current noise of the PFD and CP is-214.199 dBA/Hz @100 kHz.Furthermore,the phase noise of the PLL is-138.34 dBc/Hz @100 kHz in the test,which demonstrates that the designed PFD and CP has low current mismatch and low in-band phase noise.
分 类 号:TN433[电子电信—微电子学与固体电子学]
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