基于DDR3的大容量数据缓存与传输系统设计  

Design of Large Capacity Data Cache and Transmission System Based on DDR3

作　　者：王晨 马游春[1] 郭鑫 WANG Chen;MA Youchun;GUO Xin(North University of China,National Key Laboratory for Electronic Measurement Technology;School of Information and Communication Engineering,North University of China)

机构地区：[1]中北大学,电子测试技术国家重点实验室 [2]中北大学信息与通信工程学院

出　　处：《仪表技术与传感器》2024年第12期71-74,79,共5页Instrument Technique and Sensor

基　　金：山西省基础研究计划资助项目(20210302124198,20210302124558)。

摘　　要：为了解决目前数据存储系统中缓存深度不足、实用性不强等问题,设计了一种高性能数据缓存与传输系统方案。该系统以ZYNQ系列开发板AX7350作为驱动平台,设计了一种以FIFO级联+乒乓操作的大容量缓存方案,该方案增加了5.625 MB的缓存容量,极大提高了系统的缓存深度。通过UDP数据组帧的形式进行以太网数据收发,DDR3作为数据存储媒介。测试结果表明:该系统进行以太网数据传输时的平均丢包率为0.054%,该系统具有可靠性。In order to solve the problem of insufficient depth and poor practicability of cache in current data storage system,this paper designed a high performance data cache and transmission system scheme.In this system,ZYNQ series development board AX7350 was used as the driving platform,and a large-capacity cache scheme based on FIFO cascading+ping-pong operation was designed.The scheme increased the cache capacity of 5.625 MB and greatly improved the cache depth of the system.Ethernet data was sent and received in the form of UDP data framing,and DDR3 was served as the data storage medium.The test results show that the average packet loss rate is 0.054%during Ethernet data transmission,and the system is reliable.

关 键 词：DDR3 乒乓操作 以太网 ZYNQ FIFO级联 大容量缓存 

分 类 号：TN919[电子电信—通信与信息系统]