超大规模集成电路布图规划方法研究综述  

Research Review of Floorplanning Methodsfor Very Large Scale Integration

作　　者：史梓慧 欧阳丹彤[1,2] 张立明[1,2] SHI Zihui;OUYANG Dantong;ZHANG Liming(College of Computer Science and Technology,Jilin University,Changchun 130012,China;Key Laboratory of Symbolic Computation and Knowledge Engineering of Ministry of Education,Jilin University,Changchun 130012,China)

机构地区：[1]吉林大学计算机科学与技术学院,长春130012 [2]吉林大学符号计算与知识工程教育部重点实验室,长春130012

出　　处：《吉林大学学报(理学版)》2025年第1期139-150,共12页Journal of Jilin University:Science Edition

基　　金：国家自然科学基金(批准号:62076108,61872159,61672261).

摘　　要：综述超大规模集成电路(VLSI)布图规划方法,探讨布图规划在集成电路设计中的重要性,以及其对芯片面积、互连线长和设计周期的影响.首先,回顾集成电路技术的发展历程,强调布图规划在确定模块位置、尺寸和旋转角度中的作用.其次,详细介绍4类主要的VLSI布图规划方法:直观构造方法、分析法、迭代法和基于机器学习的方法.再次,讨论两个VLSI设计领域中常用的基准数据集MCNC和GSRC对测试和评估布图设计方法的重要性.最后,总结布图规划领域的研究进展,并指出未来的研究方向.We review the floorplanning methods for very large scale integration(VLSI),explore the significance of floorplanning in integrated circuit design,and its impact on chip area,interconnect length,and design cycle.Firstly,we review the development history of integrated circuit technology,emphasize the role of floorplanning in determining the position,size,and rotation angles of modules.Secondly,we provide a detailed introduction to four main categories of VLSI floorplanning methods:intuitive construction methods,analytical methods,iterative methods and machine learning methods.Thirdly,we discuss two commonly used MCNC and GSRC benchmark datasets,which are crucial for testing and evaluating floorplanning methods in the VLSI design field.Finally,we summarize the research progress in the field of floorplanning and point out future research directions.

关 键 词：超大规模集成电路 布图规划 布局 构造法 分析法 迭代法 机器学习方法 

分 类 号：TP391[自动化与计算机技术—计算机应用技术] TN47[自动化与计算机技术—计算机科学与技术]