四级流水线堆栈处理器研究与设计  

Research and design of four-stage pipelined stack processor

作　　者：朱恒宇 周永录 刘宏杰[1,2] 代红兵 ZHU Heng-yu;ZHOU Yong-lu;LIU Hong-jie;DAI Hong-bing(School of Information Science and Engineering,Yunnan University,Kunming 650500,China;Digital Media Technology Key Laboratory of Universities in Yunnan,Yunnan University,Kunming 650223,China)

机构地区：[1]云南大学信息学院,云南昆明650500 [2]云南大学云南省高校数字媒体技术重点实验室,云南昆明650223

出　　处：《计算机工程与设计》2025年第1期265-273,共9页Computer Engineering and Design

基　　金：国家自然科学基金项目(61962060)。

摘　　要：针对现有堆栈处理器主频较低的问题,设计一种16位的四级流水线堆栈处理器ZP16。采用冯诺伊曼结构与J1指令集,具有数据堆栈和返回堆栈两个独立堆栈。四级流水线包括取指、译码、执行和回写。通过合理的结构设计与流水线冲刷技术解决ZP16中流水线冒险问题。实验结果表明,在Xilinx XC7A100T FPGA目标芯片上,ZP16的运行主频稳定在230 MHz。与J1堆栈处理器相比,ZP16流水线加速比为1.3,资源占用率基本相当,功耗增加8%,主频提升130%。与其它同类型堆栈处理器在不同的目标芯片上进行比较,ZP16主频有较为明显的提升。To address the problem of low frequency of existing stack processors,a 16-bit four-stage pipeline stack processor ZP16 was designed.The von Neumann architecture and J1 instruction set were adopted,featuring two independent stacks for data and return addresses.The four-stage pipeline included procedures of fetch,decode,execute,and write-back.The pipeline hazards in ZP16 were solved by a reasonable structure design and pipeline flush.Experimental results show that the ZP16 runs at a stable frequency of 230 MHz on the Xilinx XC7A100T FPGA target chip.Compared with the J1 stack processor,the pipeline speedup of ZP16 is 1.3,the resource occupation rate is basically comparable,the power consumption is increased by 8%,and the frequency is increased by 130%.Compared with other processors of the same type of stack on different target chips,the ZP16 frequency has a more significant increase.

关 键 词：堆栈处理器 流水线 现场可编程门阵列 主频 加速比 资源占用率 功耗 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]